LS1046 SDRAM Multi Bits error injection.

[xiaohua_tang]

Hi,

I am trying to inject the ECC multi-bits errors, by using ECC_ERR_INJECT(EIEN:1) and DATA_ERR
_INJECT_HI (set as 0x03 for bit 0 and bit 1 invert),  DATA_ERR_INJECT_LO (0x00), but it crashes.

but it works for single bit error injection by using above registers DATA_ERR_INJECT_HI(set as 0x01 for bit 0 invert), the single bit error is detected by ERR_DETECT.

Any idea to prevent crash or other way to inject multi bits error?

[TrinathK]

Hi @yipingwang 

I didn't see address register for injecting errors at particular RAM address. If i set DATA_ERR_INJECT_HI to 0x0000_0001 (bit 0 invert), Does it invert bit-0 of all RAM addresses ?

[yipingwang · Accepted solution]

when single bit error (SBE) occur the controller corrects the error and data send back to SoC is correct and system works with no issues. And if the number of the SBE reaches the threshold counter (SBEC) the controller sends an interrupt to GIC. when multi bit error (MBE) occur the controller does not correct the error and bad data is sent back to SoC, And controller sends an interrupt to GIC. the interrupt sent to GIC for SBE and MBE is the same. so customer can develop the interrupt service routine for SBE (since the system does not crash) and then when MBE is injected the same routine would be used. ECC in LS106 is a SECDED (Single bit error correction and double bit error detection) so it does not correct any error more than SBE. usually when a system gets an MBE it needs to be reset, so a graceful reset is the best action for an MBE event.