LS1043A - is it possible to set L2-cache size from software

[LGraban]

Hi,

Is it possible to set L2-cache size from software?

I tried to find any information about that in LS1043A and Cortex-A53 documents, but with no results.

Does anyone know about some registers to set Cache size? I know about Cache-Size-ID-Register but it is ReadOnly.

Also in A53 doc L2-memory there is information about 16-way set-associative cache structure. Do you know if it's possible to deactivate some of these ways?

Thanks

[Chavira]

Thank you for contacting NXP support!

According to the documentation of ARM, the cores A53 supports 2Mb of L2 cache but the LS1043 only have 1Mb, unfortunately, the L2 cache is a hardware function and only you can get the information of the size from the registers that you mention before.

That image indicates the possibilities of the A53 core and the selection and functions for LS1043A.

You can consult that information in the Reference Manual.

[LGraban]

Thank you Chavira for your quick response.