LS1043A DDR init

[j_wallace]

Hi experts,

We have a custom LS1043A based board with two DDR4 (MT40A512M16JY-083E). I tried to generate initialization code with QCVS but it is not clear how this code may be used to replace LS1043ARDB initialization code in u-boot (board/freescale/ls1043ardb/ddr.c), which seems to be for MT40A512M8HX-093E DDR4 model.

May the controller work without the option CONFIG_SYS_DDR_RAW_TIMING?

Best regards.

[mark_xingchangy]

Hi j_wallace,

I am working on MT40A512M16JY recently. Does yours work now? From the spec of MT40A512M16JY, the n_row_addr should be 16, and bank_group_bits should be 1.

    .n_row_addr = 16,
    .n_col_addr = 10,
    .bank_addr_bits = 0,
    .bank_group_bits = 1,

Best Regards,

Mark

[j_wallace]

Hi Mark.

The first structure I showed was the LS1043ARDB one. I'm not using the Raw Timing method any more but the fixed DDR parameters method with QCVS generated code. The board is now chanting and dansing! But I have to stress-test the memory, network and so. Did you succedded with yours?

Best Regards

Wallace. 

[mark_xingchangy]

Hi Wallace,

Thanks for your reply and glad for your board to work!

I am still struggling on my board. After modifying the target ini file as the following in Codewarrior, eMMC/SD card can be flashed through CodeWarrior.

   # CS0_CONFIG
    CCSR_BE_M(0x1080000 + 0x080, 0x80010412)

But there isn't output still from console after modifying Raw Timing of ddr.c as the following.

    .n_row_addr = 16,
    .n_col_addr = 10,
    .bank_addr_bits = 0,
    .bank_group_bits = 1,

Could you help me on the two questions below?

1. Is there any UART console output before you tuning DDR parameters on your board?

2. You mentioned not using the Raw Timing method but the fixed DDR parameters method. How do you implement it? Need disable CONFIG_SYS_DDR_RAW_TIMING switch? Could you tell me more detail about how to change from Raw Timing method to fixed DDR parameters method with QCVS generated? Thanks!

Best Regards,

Mark Yang

[j_wallace]

Hi Mark,

1) Our board boots from QSPI interface. But Yes, No mater DDR parameters, I think if your RCW is correct and your bootloader flashed at the right offset your board should be able to output startup messages like u-boot version and so.

- If you are not using the default uart as the demo board, could you check your console uart is properly declared in u-boot?

- If the ASLEEP LED is cabled on your board, could you check your board has passed the Pre-boot initialization phase and is out of reset?

2) Yes, disable CONFIG_SYS_DDR_RAW_TIMING if you use fixed parameters. Look at the following link, there is an implementation of the fixed parameters method. But First, try to validate your RCW+PBI and double-check the chip errata.

git.denx.de Git - u-boot/u-boot-fsl-qoriq.git/blob - board/freescale/ls1043ardb/ddr.h 

git.denx.de Git - u-boot/u-boot-fsl-qoriq.git/blob - board/freescale/ls1043ardb/ddr.c 

Best Regards.

[mark_xingchangy]

Hi Wallace,

Thanks much for your answer!

For UART, we use the same UART1 as the EVK. That pin is only GPIO/UART functions.

For ASLEEP LED, we found it keep ON after the board powered on if SD card with correct u-boot is ON. It will be OFF if no SD card in or blank SD card in.

[j_wallace]

Hi Mark,

Maybe your ASLEEP behaviour depends on the cabling of your board... On LS1043ARDB the LED remains ON after POR if Pre-boot Initialization failed. (e.g. bad RCW or PBI or of course empty boot media).  

B.R.

[mark_xingchangy]

Hi Wallace,

Thanks much for your answer!

For debugging, the RESET_REQ was disconnected. We will reconnect the RESET_REQ late, and check if it works.

B.R.

Mark Yang

[j_wallace]

If your board boots from SDHC interface you should be able to use just the SPL to check your UART is working. SPL runs from OCRAM, so it should show some messages before hanging with full u-boot copy to SDRAM if DDR parameters are not correct.

Best Regards.

[yipingwang]

Hello j_wallace,

In u-boot, users could initialize DDR controller with reading  from SPD, DDR raw timing data and fixed DDR controller configuration register parameters 3 methods, the user could choose any method for convenience. DDR related raw timing parameters and controller configuration registers used in u-boot should been optimized and validated with DDRv tool on the target board, the user could  to use these parameters in the final DDRv project after optimization and validation.

If there is SPD on the target board, it is convenient to use reading from SPD method. Please refer to board/freescale/ls1046ardb/ddr.c, you could refer to the last section in DDR Controller Configuration on LS2085/LS2080 Bringing up for how to use DDRv tool generated parameters in u-boot.

In board/freescale/ls1043ardb/ddr.c, raw timing methods is used. In QCVS(DDRv project), after optimization and validation with DDRv tool, the user could get the final DDR raw timing parameters in the properties panel in QCVS project, users could use these parameters in u-boot to configure DDR controller with raw timing parameters.

For using fixed DDR controller registers configuration parameters method, the user could refer to board/freescale/p1010rdb/ddr.c, the user could use values generated in uboot_ddr1.c file in Generated_Code folder of the QCVS project.

Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[j_wallace]

Hi there,

Thanks a lot. Let me sutdy this material and give you feedback.

Regards.

[j_wallace]

Hi,

Good news, our board is now booting but hangs on DDR initialization with the following message:

--------------------------------------------

DRAM:  Initializing DDR....
Detected UDIMM Fixed DDR on board
DDR clock (MCLK cycle 1667 ps) is slower than DIMM(s) (tCKmax 1500 ps) can support.

--------------------------------------------

I am trying to use Raw Timing method since my u-boot code is derived from LS1043ARDB. We have generated DDR parameters using QCVS but it looks like parameters are not directly usable :

1) In QCVS I have CAS Lentency (tCL) = 17 clocks / 21.2ns . How this value is related to the parameter in u-boot (caslat_x  in the following structure). Our board has MT40A512M16JY-083E DDR4.

Best Regards

dimm_params_t ddr_raw_timing = {
    .n_ranks = 1,
    .rank_density = 2147483648u,
    .capacity = 2147483648u,
    .primary_sdram_width = 32,
    .ec_sdram_width = 0,
    .registered_dimm = 0,
    .mirrored_dimm = 0,
    .n_row_addr = 15,
    .n_col_addr = 10,
    .bank_addr_bits = 0,
    .bank_group_bits = 2,
    .edc_config = 0,
    .burst_lengths_bitmask = 0x0c,

    .tckmin_x_ps = 938,            
    .tckmax_ps = 1500,            
    .caslat_x = 0x000DFA00,     
    .taa_ps = 13500,
    .trcd_ps = 13500,
    .trp_ps = 13500,
    .tras_ps = 33000,
    .trc_ps = 46500,
    .trfc1_ps = 260000,
    .trfc2_ps = 160000,
    .trfc4_ps = 110000,
    .tfaw_ps = 21000,
    .trrds_ps = 3700,
    .trrdl_ps = 5300,
    .tccdl_ps = 5355,
    .refresh_rate_ps = 7800000,
    .dq_mapping[0] = 0x0,
    .dq_mapping[1] = 0x0,
    .dq_mapping[2] = 0x0,
    .dq_mapping[3] = 0x0,
    .dq_mapping[4] = 0x0,
    .dq_mapping[5] = 0x0,
    .dq_mapping[6] = 0x0,
    .dq_mapping[7] = 0x0,
    .dq_mapping[8] = 0x0,
    .dq_mapping[9] = 0x0,
    .dq_mapping[10] = 0x0,
    .dq_mapping[11] = 0x0,
    .dq_mapping[12] = 0x0,
    .dq_mapping[13] = 0x0,
    .dq_mapping[14] = 0x0,
    .dq_mapping[15] = 0x0,
    .dq_mapping[16] = 0x0,
    .dq_mapping[17] = 0x0,
    .dq_mapping_ors = 0,
};

[j_wallace]

I enabled debug messages and It looks like DDR Init completes without error but u-boot hangs after relocation.

---------------------------------------------------------------------------------------------------------------------------------------------

U-Boot 2017.09-rc1 (Jul 06 2018 - 09:23:46 +0200)

initcall: 00000000401139b0
U-Boot code: 40100000 -> 40182190  BSS: -> 401BD2D0
initcall: 000000004010319c
SoC:  unknown (0x87920311)
Clock Configuration:
       CPU0(A53):1200 MHz  CPU1(A53):1200 MHz  CPU2(A53):1200 MHz
       CPU3(A53):1200 MHz
       Bus:      300  MHz  DDR:      1600 MT/s
Reset Configuration Word (RCW):
       00000000: 0610000c 0a000000 00000000 00000000
       00000010: 14550002 80004012 40025000 c1002000
       00000020: 00000000 00000000 00000000 00038800
       00000030: 20004500 00001100 00000096 00000001
initcall: 00000000401140c8
initcall: 0000000040113b8c
I2C:   ready
initcall: 0000000040113b6c
DRAM:  initcall: 000000004010365c
Initializing DDR....
starting at step 1 (STEP_GET_SPD)
Filling dimm parameters from board specific file
Computing lowest common DIMM parameters for memctl=0
Detected UDIMM Fixed DDR on board
lowest_common_spd_caslat is 0xb
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 938
trcd_ps   = 13500
trp_ps    = 13500
tras_ps   = 33000
trfc1_ps = 260000
trfc2_ps = 160000
trfc4_ps = 110000
trrds_ps = 3700
trrdl_ps = 5300
tccdl_ps = 5355
twr_ps    = 15000
trc_ps    = 46500
compute_lowest_common_dimm_parameters: Passed
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
Found timing match: n_ranks 1, data rate 1666, rank_gb 0
0 of 1 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x80000000
Total mem by __step_assign_addresses is 0x80000000
Total mem 2147483648 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x0000007f
FSLDDR: cs[0]_config = 0x80040322
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: cs[1]_bnds = 0x00000000
FSLDDR: cs[1]_config = 0x00000000
FSLDDR: cs[1]_config_2 = 0x00000000
FSLDDR: cs[2]_bnds = 0x00000000
FSLDDR: cs[2]_config = 0x00000000
FSLDDR: cs[2]_config_2 = 0x00000000
FSLDDR: cs[3]_bnds = 0x00000000
FSLDDR: cs[3]_config = 0x00000000
FSLDDR: cs[3]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x91550018
FSLDDR: timing_cfg_3 = 0x010c1000
FSLDDR: timing_cfg_1 = 0xbbb48c42
FSLDDR: timing_cfg_2 = 0x0048c111
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x0000a181
FSLDDR: ddr_sdram_cfg = 0xc50c0008
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x00401100
FSLDDR: ddr_sdram_mode = 0x03010210
FSLDDR: ddr_sdram_mode_3 = 0x00010210
FSLDDR: ddr_sdram_mode_5 = 0x00010210
FSLDDR: ddr_sdram_mode_5 = 0x00010210
FSLDDR: ddr_sdram_mode_2 = 0x00000000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_mode_9) = 0x00000500
FSLDDR: ddr_sdram_mode_11 = 0x00000400
FSLDDR: ddr_sdram_mode_13 = 0x00000400
FSLDDR: ddr_sdram_mode_15 = 0x00000400
FSLDDR: ddr_sdram_mode_10) = 0x04000000
FSLDDR: ddr_sdram_mode_12 = 0x04000000
FSLDDR: ddr_sdram_mode_14 = 0x04000000
FSLDDR: ddr_sdram_mode_16 = 0x04000000
FSLDDR: ddr_sdram_interval = 0x18600618
FSLDDR: clk_cntl = 0x03000000
FSLDDR: timing_cfg_4 = 0x00000002
FSLDDR: timing_cfg_5 = 0x03401400
FSLDDR: ddr_sdram_cfg_3 = 0x00000000
FSLDDR: timing_cfg_6 = 0x00000000
FSLDDR: timing_cfg_7 = 0x13300000
FSLDDR: timing_cfg_8 = 0x02115600
FSLDDR: timing_cfg_9 = 0x00000000
FSLDDR: dq_map_0 = 0x00000000
FSLDDR: dq_map_1 = 0x00000000
FSLDDR: dq_map_2 = 0x00000000
FSLDDR: dq_map_3 = 0x00000000
FSLDDR: zq_cntl = 0x8a090705
FSLDDR: wrlvl_cntl = 0x8675f607
FSLDDR: wrlvl_cntl_2 = 0x07090800
FSLDDR: wrlvl_cntl_3 = 0x00000000
Programming controller 0
Write to debug_29 as 00700046
total 2 GB
Need to wait up to 132 * 10ms
total_memory by __fsl_ddr_sdram = 2147483648
addr=80000000 level=1
idx=2 PTE 0000000010000010 at level 1: 60000080000621
Set attrs=0 pte=0000000010000010 level=1
addr=c0000000 level=1
idx=3 PTE 0000000010000018 at level 1: 600000c0000621
Set attrs=0 pte=0000000010000018 level=1
addr=80000000 level=1
idx=2 PTE 0000000010000010 at level 1: 80000620
Set attrs=231 pte=0000000010000010 level=1
addr=c0000000 level=1
idx=3 PTE 0000000010000018 at level 1: c0000620
Set attrs=231 pte=0000000010000018 level=1
initcall: 0000000040113d40
Monitor len: 000BD2D0
Ram size: 80000000
Ram top: FFE00000
initcall: 0000000040113838
initcall: 0000000040113afc
TLB table from ffdf0000 to ffe00000
initcall: 0000000040113c2c
initcall: 0000000040113c34
initcall: 0000000040113960
Reserving 756k for U-Boot at: ffd32000
initcall: 000000004011392c
Reserving 1032k for malloc() at: ffc30000
initcall: 0000000040113aa0
Reserving 168 Bytes for Board Info at: ffc2ff58
initcall: 0000000040113c3c
initcall: 00000000401138f0
Reserving 472 Bytes for Global Data at: ffc2fd80
initcall: 0000000040113880
Reserving 10016 Bytes for FDT at: ffc2d660
initcall: 0000000040113c44
initcall: 0000000040113c1c
initcall: 0000000040113dbc
initcall: 00000000401034a8
initcall: 0000000040113c54

RAM Configuration:
Bank #0: 80000000 2 GiB
Bank #1: 0 0 Bytes

DRAM:  2 GiB (DDR4, 32-bit, CL=11, ECC off)
initcall: 000000004011385c
New Stack Pointer is: ffc2d650
initcall: 0000000040113a5c
initcall: 0000000040113c4c
initcall: 00000000401139e4
Relocation Offset is: bfc32000
Relocating to ffd32000, new gd at ffc2fd80, sp at ffc2d650

----------------------

Nothing after this message

[ufedor]

Please refer to the following Community thread:

https://community.nxp.com/message/815388?commentID=815388#comment-815388