Hello,
I'm trying to understand the reset sequence timing from the LS1028A Reference Design Board. I ran the simulation using the provided code and tested the LS1028A RDB at the lab. Both showing that the DUT_PORESET_B signal remain asserted for about 2.5 second.
From the LS1028 A reference manual page 143, PORESET_B assertion time requires 32 SYSCLK clocks, and from the LS1028A data sheet page 75, required assertion time of PORESET_B after all supply rails are stable is 1.0 ms minimum.
Assuming SYSCLK is 100MHz, 32 SYSCLK cycles is only 320 ns.
Why does the LS1028A RDB assert PORESET_B for so long (about 2.5 second)?
Thanks.
