LS1028 - RCW generation to boot from I2C EEPROM to NOR Flash

[kumar_086]

Dear Experts,

I started with the LS1028A processor EVM which booted with the onboard NOR flash images.

Now, booting from I2C EEPROM [RCW] and jumping to NOR Flash [U-Boot Image] is required. How to specify this in RCW PBI commands?

Please help!

[yipingwang]

Add this block copy command in end in the RCW+PBI binary
blockcopy 0x0a,0x400,0x00100000,0x9400
Source : I2C EEPROM = 0xa
Source address: 0x400
Destination address: OCRAM (0x100000)
Block size : size of BL2 binary in bytes

Generate the full firmware image for ls1028a. The below-mentioned files will be generated.
Program the following files in their respective locations
1. RCW+PBI binary -- I2C EEPROM at 0x0 (rcw_1500_gpu600.bin present in <flexbuild_dir>/packages/firmware/rcw/ls1028ardb/R_SQPP_0x85bb)
2. BL2 binary -- I2C EEPROM at 0x400 (bl2.bin present in <flexbuild_dir>/packages/firmware/atf/build/ls1028ardb/release)
3. FIP binary -- NOR flash at 0x10000 (fip.bin present in <flexbuild_dir>/packages/firmware/atf/build/ls1028ardb/release)

[kumar_086]

Dear @yipingwang ,

The I2C EEPROM programmed with the file's path (RCW+PBI, BL2) specified NOR Flash with FIP.bin. The RCW was added with block copy command.

Read back and verified the I2C EEPROM and NOR flash contents are proper. Changed the RDB SW2 [1:4]: '1010'b. There were no prints observed after the power cycle of RDB board.

Also, tried changing the RCW block copy command destination of OCRAM address from 0x100000 to 0x1800D000 as per the reference manual. There were no prints observed after the power cycle of RDB board.

Please help.

Thanks

Kumar

[yipingwang]

I am trying this on my end.
Meanwhile, Would you please share your RCW and PBL file?

[yipingwang]

I have tried to boot using I2C. I am able to boot successfully. Attached the files for your reference.
Change the switch settings and wait for some secs as I2C is lower as compared to Flexspi.

Here are the updated steps:
1. Add the following commands at the end in rcw_1500_gpu600.rcw file
.pbi
write 0x01e00400,0x1800d000
blockcopy 0xa,0x400,0x1800d000,0x9435
.end

CCSR write command:
setting boot location pointer to 0x1800d000 in Boot location pointer low-order address (BOOTLOCPTRL) register present in DCFG.
block copy command:
blockcopy 0x0a,0x400,0x00100000,0x9400
Source : I2C EEPROM = 0xa
Source address: 0x400
Destination address: OCRAM (0x100000)
Block size : size of BL2 binary in bytes

2. Generate the files and program at the respective locations:
3. RCW+PBI binary -- I2C EEPROM at 0x0 (rcw_1500_gpu600.bin)
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/rcw/ls1028ardb$ make
python3 ../rcw.py -i R_SQPP_0x85bb/rcw_1500_gpu600.rcw -o R_SQPP_0x85bb/rcw_1500_gpu600.bin
(for flexbuild versions before 2108: <flexbuild_dir>/packages/firmware/rcw/ls1028ardb/ R_SQPP_0x85bb/)

4. BL2 binary -- I2C EEPROM at 0x400
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ export ARCH=arm64
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ export CROSS_COMPILE=aarch64-linux-gnu-
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ make distclean
REALCLEAN
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ make PLAT=ls1028ardb BOOT_MODE=flexspi_nor pbl RCW=/home/nxf65210/data/work/ls_series/flexbuild_lsdk2108/components/firmware/rcw/ls1028ardb/R_SQPP_0x85bb/rcw_1500_gpu600.bin

bl2.bin present in /flexbuild_lsdk2108/components/firmware/atf/build/ls1028ardb/release/bl2.bin
(for flexbuild versions before 2108: <flexbuild_dir>/packages/firmware/atf/build/ls1028ardb/release)

5. FIP binary -- NOR flash at 0x100000
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108$ flex-builder -c atf -m ls1028ardb -b xspi
(flexbuild_lsdk2004_update_290520/build/firmware/atf/ls1028ardb/fip_uboot.bin)

(for flexbuild versions before 2108: fip.bin present in <flexbuild_dir>/build/firmware/atf/ls1028ardb/)

Programming EEPROM using I2C on U-Boot on LS1028ARDB
=> i2c probe
Valid chip addresses: 00 50 52 53 57 66 67 77 7C
=> i2c write 0xa0000000 0x50 0.2 0x11c
=> i2c read 0x50 0.2 0x114 0xc0000000
=> i2c write 0xa0000000 0x50 0x400.2 <size of bl2.bin>

[kumar_086]

Hello @yipingwang 

Thank you for the detailed instructions.

We have followed them and created the files as mentioned, programmed them to I2C EEPROM & NOR Flash, changed the boot switch for I2C boot, and observed no console prints on the terminal.

Attached are the test files generated. Please help us if we are missing any or any other DIP SW changes to be done in RDB.

Regards

Kumar

PS: Apologies for the delayed reply due to the work break.

[kumar_086]

Dear @yipingwang,

The shared files rcw_1500_gpu600.rcw and rcw_1500_gpu600.bin were added with the pbi commands. In rcw_1500_gpu600.bin we could see the write and block copy instructions at offset 0x8C - 0xA3. 

Regards

Kumar

[yipingwang]

I agree customer have added the block copy command but these commands have to be added at the end of .rcw file after WA of errata.

[yipingwang]

Customer has not added the block copy pbi command like this.
****************************
SRDS_PRTCL_S1_L2=11
SRDS_PRTCL_S1_L3=11

/* Errata for PCIe controller */
#include <../ls1028asi/a008851.rcw>
#include <../ls1028asi/a010477.rcw>
#include <../ls1028asi/a009531.rcw>

/* Increase FSPI clock frequency */
#include <../ls1028asi/fspi_speed.rcw>

.pbi
write 0x01e00400,0x1800d000
blockcopy 0xa,0x400,0x1800d000,0xB000
.end
**********************************

[kumar_086]

Dear @yipingwang 

Thanks for mentioning it.

Changed the placement of the pbi commands, and generated a new RCW as attached with this. Programmed it in EEPROM along with bl2.bin and fip.bin in flash. When we restart the board with I2C boot settings no prints were observed on the terminal.

Is it possible to identify where the processor is stuck? during RCW fetching or bl2 fetching using code warrior? (if so, request you to share the steps)

Please help to make the I2C boot successful. Thanks

[yipingwang]

I am trying these files on my end to debug the issue further.
Meanwhile, customer can use CCS commands to know the status whether RCW or PBI is loaded or not.
Refer section 4.3.1 RST_CCSR memory map in LS1028ARM,
RCW Completion Registe, PBI Completion Register shows the status.
Please ak then to share the value of these registers.
**************************
(bin) 49 % delete all
(bin) 50 % config cc cwtap:10.224.117.42<ip_address> //if USB used write nothing
(bin) 51 % show cc
0: CodeWarrior TAP (cwtap:10.224.117.42) CC software ver. {0.0}
(bin) 53 % ccs::config_chain {ls1028a dap}
(bin) 54 % display ::ccs::get_config_chain
(bin) 66 % display ccs::read_mem 3 0x1E60100 4 0 0x10

[kumar_086]

Dear @yipingwang,

We have tried the following on RDB for I2C Booting,

1.  Loaded EEPROM with rcw, bl2.bin and flash with fip.bin provided by you; rebooted the board by changing SW2[1:4] - 1010: UEFI/I2C Boot EEPROM; but no prints were observed on UART console
2. Generated the files by adding the pbi commands in rcw as shared above and loaded EEPROM with rcw, bl2.bin, and flash with fip.bin; rebooted the board by changing SW2[1:4] - 1010: UEFI/I2C Boot EEPROM; but no prints were observed on UART console
3. Suspected whether the processor is able to access EEPROM on power-on or not, and observed that EEPROM SDA pin (u47.5) no activity is observed when SW2[1:4] - 1010 - I2C Boot
4. Changed the booting to eMMC and issued i2c probe command at U-Boot, we are able to see the I2C transactions on the EEPROM SDA pin (u47.5)
5. We observed that the files which you shared have the BOOT_LOC (RCW bits 263-260) as 0x1A (XSPI), but it needs to be 0x15 (OCRAM) as per the data sheet, right? However, we tried with both settings but it didn't boot

With the above observations, we noted that RDB LS1028A is not accessing the EEPROM with the selected SW2[1:4] - 1010 - I2C Boot pins. Do we need to enable any jumpers or any DIP SW settings related to I2C Boot? Please share.

Apologies for the delayed reply. Looking forward to your valuable inputs to progress on this I2C EEPROM booting.

Regards

Kumar

[kumar_086]

Dear @yipingwang ,

We'd want to discuss our findings after testing this I2C booting in our unique LS1028a board. 

We adhered to the guidelines provided in order to edit rcw, build atf, and programme output images into I2C EEPROM & Flash memory.

The findings are as follows:

• Based on the prints, we can tell that the processor jumps to the I2C EEPROM and fetches RCW and BL2.
• After this, we were anticipating BL31 and U-Boot prints, but they didn't arrive.

We attempted to load the Flexbuild versions 2012, 2108, and the files you shared.

The uart output of the processor,

• Flexbuild v2012

  • ERROR:   Boot Device detection failed, Check RCW_SRC

    NOTICE:  Fixed DDR on board

    NOTICE:  4 GB DDR4, 32-bit, CL=11, ECC on
    NOTICE:  BL2: v1.5(release):LSDK-20.12-dirty
    NOTICE:  BL2: Built : 18:58:25, Feb 3 2023

• Flexbuild v2108

  • NOTICE:  Fixed DDR on board

    NOTICE:  4 GB DDR4, 32-bit, CL=11, ECC on
    ERROR:   Boot Device detection failed, Check RCW_SRC
    NOTICE:  BL2: v2.4(release):
    NOTICE:  BL2: Built : 12:37:14, Feb 14 2023

• Images shared in this thread by you

  • NOTICE:  Fixed DDR on board

    NOTICE:  4 GB DDR4, 32-bit, CL=11, ECC on
    ERROR:   Boot Device detection failed, Check RCW_SRC
    NOTICE:  BL2: v2.4(release):LSDK-21.08-0-g340b20bcb
    NOTICE:  BL2: Built : 16:58:13, Jun 20 2022

The files for flexbuild versions 2012 and 2108—the.rcw, rcw.bin, bl2.bin, and fip.bin—are attached to this thread.

Please contribute your ideas so that we can successfully boot the i2c eeprom.

Regards

Kumar

[kumar_086]

Dear @yipingwang ,

We are awaiting for your inputs.

Thanks

[kumar_086]

Dear @yipingwang ,

Could you please let us know if the U-Boot is booting when I2C EEPROM is selected as the boot device?

Thanks 

[kumar_086 · Accepted solution]

Dear All,

Happy to share that I2C EEPROM booting is working for the LS1028A processor using Flexbuild LSDK V21.08.

By default, this source is not supported to read RCW from I2C EEPROM and needs to modify the PORSR1 in drivers/nxp/dcfg/dcfg.c; read_reg_porsr1().

With this change, it started working.

Thank you @yipingwang for your support on this.

Regards

Kumar ; 130162687

[yipingwang]

1. Add the following commands at the end in rcw_1500_gpu600.rcw file
.pbi
write 0x01e00400,0x1800d000
blockcopy 0xa,0x400,0x1800d000,0x9435
.end

The rcw file shared by customer does not contain these additional PBI writes at the end.
Add these commands after all errata WA.
Let me know the results after this.

[kumar_086]

Dear @yipingwang,

Thank you for sharing these details.

The LS1028ardb schematics mention that there is an i2c hub between processor and i2c eeprom. Also this hub gets activated only when the control register is programmed, on power on hub is deactivated. 

Can you please clarify the following,

1. Does i2c boot supported by this RDB?

2. Is FIP binary start address possible to change or is it always pointed to NOR Flash 0x10000?
3. Is it possible to customize the RCW from flexbuild?

Thanks

Kumar

[yipingwang]

1. Does i2c boot supported by this RDB?

Yes, I2C boot is supported by LS1028ARDB There is an i2c hub (PCA9847PWJ) between processor and i2c eeprom. RST_I2CMUX_B signal is for resetting it. This signal is asserted when LS1028A PORESET_B is asserted. The system controller manages the reset sequencing during the system startup. Therefore, after power on i2c hub is activated.

2. Is FIP binary start address possible to change or is it always pointed to NOR Flash 0x10000?

Yes.

Refer Table 22. Unified 64 MiB memory layout of NOR/QSPI/XSPI/NAND/SD media for composite firmware on all Layerscape platforms in Layerscape Software Development Kit User Guide, Rev. 21.08, 24 January 2022.

3. Is it possible to customize the RCW from flexbuild?

Yes.

rcw_1500_gpu600.rcw present in <flexbuild_dir>/packages/firmware/rcw/ls1028ardb/R_SQPP_0x85bb is can be modified by user.

Value of RCW fields are written in decimal.

Then Run the following commands:

$ cd flexbuild_<verison>

$ source setup.env

$ flex-builder -c atf -m ls1028ardb<machine> -b xspi<boot source>

RCW+PBI binary -- I2C EEPROM at 0x0 (rcw_1500_gpu600.bin present in

RCW+<flexbuild_dir>/packages/firmware/rcw/ls1028ardb/R_SQPP_0x85bb)

BL2 binary -- I2C EEPROM at 0x400 (bl2.bin present in <flexbuild_dir>/packages/firmware/atf/build/ls1028ardb/release)

FIP binary -- NOR flash at 0x10000 (fip.bin present in <flexbuild_dir>/packages/firmware/atf/build/ls1028ardb/release)

[kumar_086]

Dear NXP Team,

Please help!