LS1012 PORESET TIME

[mipetouris]

Hello,

at  the power up stage of the ls1012 the required assertion time of the poreset signal is 100mS.

Which is the requesting time of assertion of the poreset signal, at the reboot/sw reset operation?

BR

Miltos

[mipetouris]

Dear Fedor

About the PORESET we know that the specs don't order other assertion time thats why we ask, while other nxp CPUs

has a time for soft reset. Please ask silicon engineer to give as an unswer. it is very important issue

For the xtal pin even if the logical move is to left it unconnected, in the datasheet nxp give guidance to  ground the pin. Are you intend to fix the specs. We need a official answer.

BR

Miltos

[ufedor]

Please create a Technical Case:

1)    open www.nxp.com
2)    Select "Support" -> "All Support Options"
3)    Click "Go to Tickets"
4)    Log in with your NXP login and password
5)    On the "Group, Create and View your support cases" page press "+ Add a new case" to start the process.

[mipetouris]

Dear ufedor,

Thank you for your patient.

I am worry about the answer because we have 1k pcs at the field with 10uS PORESET_B and all works perfect.

and there is and other issue. About the XTAL pin (pin 87) nxp propose to ground the pin if unused.

we are left it unconnected.

So for the PORESET issue when power up the cpu the assertion time is 180mS. the 10us is when we are doing software reset and all the powers are stable. 

for the XTAL pin why there is need to ground it? since it is output pin for crystal use.

BR

Miltos

[ufedor]

In the processor's Data Sheet it is written:

"Required assertion time of PORESET_B after VDD is stable 100 ms"

This means that the assertion time can't be smaller than 100 ms during the power-on.

When the VDD is stable the assertion time can be 100 ms.

Other assertion timings were not characterized.

> for the XTAL pin why there is need to ground it? since it is output pin for crystal use.

I agree that XTAL can be left unconnected.

[ufedor]

The PORESET_B assertion time in the described case is 100ms.

[mipetouris]

Even if the Power rails are stable and do sw reset of the cpu you need 100ms?

for the moment in the sw reset operation the assertion time of my board is set to be 10us 

and  the cpu operates stable.

[ufedor]

NXP guarantees normal processor operation if the PORESET_B assertion time in the described case is 100ms.