Hi,
After looking through all your question, I can preliminarily know what you would like to do. Let me summarize from the platform point of view:
First, the CPC L3 Cache or part of CPC could not be designated for any core, it's platform shared resource.
Second, the way for this is using different physical address range.
To be specific, use different partition control registers and LAW for each part of address range for this purpose.
Please refer to Section 8.3.1.2 Partitioning Control Registers and Section 2.4 Local Access Window.
For example, for two cores core A and core B:
Core A will access DDR part A, core B will access DDR part B;
Core A use CPCPIRa/CPCPARa/CPCPWRa and LAWa, core B use CPCPIRb/CPCPARb/CPCPWRb and LAWb
LAWa is for DDR part A, LAWb is for DDR part B.
In LAWa, the CSD_ID equals the PID bit set in CPCPIRa, assume it's PIDa, the CPCPARa allow this type of transaction to be allocated in one of the ways defined in CPCPWRa, in CPCPWRa, you give four ways a0,a1,a2,a3 for example, lets say it's CPC part A.
Similarly setting those in LAWb. You need to give different PID, for example PIDb, and different ways b0, b1,b2,b3, lets say it's CPC part B.
Thus when cache miss happens on Core A, as it's accessing DDR part A, it will find in the 16 triples of partition control registers and find a match CSD_ID/PID in CPCPIRa, then allocate CPC part A with replacement algorithm. You need to make sure Core A only access DDR part A, if it access DDR part B, as registers CPCPIRb/CPCPARb/CPCPWRb and LAWb are also visible to Core A for those are all device level, it will find match CSD_ID/PID, and resulting in allocation in CPC B as well. That's why you could not make any part of CPC as private to any core.
It's a little complicated. Fortunately as Scott have suggested in your other thread you can do that in hv config tree
How does the L3 cache mapping to memory in P4080DS, how the address was translated?
Also you can do this in CodeWarrior by yourself. I hope I have made the description as clear as possible I could.
Have a great day,
Lunmin
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