Hello!
We are using P1010 with BSP v1.3, tests done on fsl rdb board.
When booting from IFC the SDHC interface is disabled, this seems to be a known limitation.
There are documents explaining how to enable SDHC interface on SPI boot mode.
Is that also possible on IFC boot mode?
We only need to access SDHC interface after boot, just for data storage purposes.
As per previous consultation with product engineering, it doesnt seem we have a hardware chip limitation for using both interfaces at the same time.
The kernel boot log is below.
Thanks!
Bruno
NAND boot...
NAND boot... WARNING: ECC not checked in SPL, check board cfg
U-Boot 2011.12-00064-gbfb0c9a (Jun 15 2012 - 00:25:55)
CPU: P1010E, Version: 1.0, (0x80f90010)
Core: E500, Version: 5.1, (0x80212151)
Clock Configuration:
CPU0:800 MHz,
CCB:400 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), IFC:100 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: P1010RDB
I2C: ready
SPI: ready
DRAM: DIMM 0: is not a DDR3 SPD.
16 MiB (DDR3, 32-bit, CL=5, ECC off)
Flash: 32 MiB <------
L2: 256 KB enabled
NAND: 32 MiB
....
linux kernel loading:
loop: module loaded
fsl-ifc ffe1e000.ifc: IFC Set Information for bank 0
NAND device: Manufacturer ID: 0xec, Chip ID: 0x75 (Samsung NAND 32MiB 3,3V 8-bit) <--------- NAND is detect correctly.
Scanning device for bad blocks
Bad eraseblock 222 at 0x000000378000
IFC NAND device at 0xff800000, bank 0
...
EDAC MC: Ver: 2.1.0
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman <----------------- SDHC not detected.
usbcore: registered new interface driver usbhid
....