DDRCLK!

[qammarabbas]

Hi,

I am interfacing DDR3L with T1042. According to the reference manual of T1042, the DDR Memory Controller needs a dedicated clock (DDRCLK) for its working. What should be the frequency of my clock if i want a maximum data transfer rate of 1600 MT/s?

[ufedor]

The DDR controller could be clocked either by DIFF_SYSCLK or DDRCLK - please refer to the QorIQ T1040 Reference Manual, 4.6.7.1.1 Single oscillator source reference clock mode:

"The RCW[DDR_REFCLK_SEL] bit is used to select clock input (DIFF_SYSCLK or DDRCLK) to the DDR PLL."

After selecting the clock source the DDR controller operation frequency is determined by RCW[MEM_PLL_RAT] - refer to the RM, Table 4-11. RCW Field Descriptions.

For example, if selected clock frequency is 100 MHz, then for 1600 MT/s data rate:

RCW[MEM_PLL_RAT] = 010000 (16:1)

Refer to the QorIQ T1040, T1020 Data Sheet, 4.1.9.3 DDRCLK and DDR data rate frequency options.