Core e500, L1 MMU load time

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Core e500, L1 MMU load time

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guillaumechevil
Contributor II

The e500 core has a two level MMU.

How can we estimate the time taken to load a L2 TLB entry in L1 MMU ?

Thank you.

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LPP
NXP Employee
NXP Employee

Please, refer to e500mcrm Section 10.3.1.1 "L1 and L2 TLB Access Times".

http://cache.freescale.com/files/32bit/doc/ref_manual/E500MCRM.pdf

"The L1 TLB arrays are checked for a translation hit in parallel with the on-chip L1 cache lookups and incur no penalty on an L1 TLB hit. If the L1 TLB arrays miss, the access proceeds to the L2 TLB arrays. For L1 instruction address translation misses, the L2 TLB latency is at least 5 clocks; for L1 data address translation misses, the L2 TLB latency is at least 5 clocks. These access times may be longer, depending on arbitration performed by the L2 arrays for simultaneous instruction L1 TLB misses, data L1 TLB misses, the execution of TLB instructions, and TLB snoop operations (snooping of TLB invalidate operations from tlbivax instructions on CoreNet)."


Have a great day,
Pavel

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