I am checking for DDR4 of LS1046A.
Sometimes, my custom board is occur read error.
I find out "read delay chain block" in DDR controller module.
Can I change delay setting of that block, or this delay value is fixed?
Looking at the current DDR read result, since reading sometimes fails, I wanted to change the timing of latching the read data.
I understand that it will delay 1/4 clock in the delay block.
I will carefully check the waveform.
Thank you for your reply.
Is there information in the reference manual as to how long it will be delayed by that delay block?
How do you adjust the timing of reading?
If the lengths of DQ and DQM are the same, is it not necessary to adjust?
> How do you adjust the timing of reading?
What do you mean?
When data is read from DDR SDRAM it is provided synchronously with DQS:
so, simplifying, the DDR controller has to delay the DQS by 1/4 of CK cycle (T/4) to shift the DQS edges to the middle of data beats.