I am trying to configure the CCI-400 to enable cache coherency.
I have a FPGA writing data to DDR and I am reading it from CPU [A72] in LS1046A.
But the cache does not get updated after the FPGA writes data to it. But if I invalidate the cache inbetween, it works fine.
I see that I am not able to configure any registers of CCI-400 [probably they are secure only registers and uboot leaves me in EL2].
Is there anyway I can check if the CCI works fine and maintain cache coherency.
It was some time ago, so I actually had to check what I did.
In my case the CCI configuration was OK. I could also check it with U-boot which allowed me to enter in EL3. MMU configuration was also OK. The issue was in our test, I did not have a sync barrier between 'FPGA writing to memory' and 'CPU reading from memory'. So the instructions were executed out of order and read from memory was faster than write to FPGA. When I disabled cache, read from DDR was slow enough for FPGA to finish writing.
Sync barrier [both data and instruction] helped in my case.
It depends on what you actually want to do.