Not possible Flash U-boot via Codewarrior when ECC 4 bits is enabled at hardware

[ds_simoes]

Hello!
I have a custom board based in BSC9132QDS. One changes is new part of NAND MT29F4G08ABA that actually works well. But now, a new feature (ECC) is necessary and some modifications on uboot and hardware are necessaries to achieve it, and were mapped as follow:

uboot:

* include/configs/bsc9132qds

#define CONFIG_SYS_NAND_CSOR    ( CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
    | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
    | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
    | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
    | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
    | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
    | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/‍‍‍‍‍‍‍‍‍‍‍‍‍‍

* hardware

   BSC9132 QDS SW7 "IFC"
   IFC ECC (cfg_ifc_ecc[0:1])
   2'b10 - 4-bit correction

I used Codewarrior PA 10.3 and USB-TAP to flash the u-boot-nand.bin, but just if SW7 2'b00 (ECC disabled) is set. When I change to SW7 2'b10 (4 - bit correction) the following error message is showed:

Failed to reset the target
[CCS last error: p1010: Core not responding ](CCSProtocolPlugin)
Error: Connect Failed.
Error executing task BSC9132QDS_NAND_FLASH.
Error:  Connect Failed.    log: Timestamp:  Thu Oct 10 09:34:08 2019

Why it is happen and how can I fix the Codewarrior's project to flash uboot on the target the board even using the SW7 2'b10 (4 - bit correction)?

Regards

[ds_simoes]

Hi community!

Someone else may help me with these questions?
Daniel Simões

[yipingwang]

Would you please provide capture CodeWarrior log to me to do more investigation?

Before connect to the target, please enable CCS log from "Run->Debug Configurations-><project>-core0_RAM_-Attach->Edit...->Advanced->Advanced CCS setting->Enable logging", and connect to the target from "Run->Debug Configurations-><project>-core0_RAM_-Attach->Debug”, the CCS log will be printed in the console panel in CodeWarrior IDE.

Note: Please open the console panel from Window->Show View->Console, and if nothing displayed, please choose the correct session on the right top icon in the panel.If the CCS log in the console is truncated, please enlarge the console buffer from Window->Preferences->Run/Debug->Console->uncheck "Limit console output".

[ds_simoes]

Hello Yiping Wang! Thanks to reply so quickly.

I enabled the ECC log how you mentioned and the console reported:

ccs_open
 ipaddr = 127.0.0.1
 port = 41475
 timeout = 15
 serverh = 0
 ccs_open; ccs_error = 0
ccs_get_connection_count
 serverh = 0
 count = 1
 ccs_get_connection_count; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_cc_version
 serverh = 0
 cc = 0
 version.major = 1
 version.minor = 3
 ccs_cc_version; ccs_error = 0
ccs_set_timeout
 serverh = 0
 timeout = 15
 ccs_set_timeout; ccs_error = 0
ccs_config_server
 serverh = 0
 cc = 0
 server_config = 0
 value = 10230
 ccs_config_server; ccs_error = 0
ccs_get_config_chain
 serverh = 0
 device_list: (size = 0)
 ccs_get_config_chain; ccs_error = 0
ccs_config_chain
 serverh = 0
 cc = 0
 device_list: (size = 1)
  device[0]:: core_type=mpc9132(202)
 ccs_config_chain; ccs_error = 0
ccs_get_config_chain
 serverh = 0
 device_list: (size = 3)
 ccs_get_config_chain; ccs_error = 0
ccs_get_config_chain
 serverh = 0
 device_list: (size = 3)
  device[0]:: core_type=mpc9132(202)
  device[1]:: core_type=p1010(219)
  device[2]:: core_type=p1010(219)
 ccs_get_config_chain; ccs_error = 0
ccs_core_run_mode
 coreh = [serverh:0;cc_index:0;chain_pos:1]
 mode = 4
 ccs_core_run_mode; ccs_error = 5
 Error message: Core not responding
ccs_close
 serverh = 0
 ccs_close; ccs_error = 0‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Thank you so much for helping me with this question and let me know if any more logging will be required.
Best regards.

[yipingwang]

Hello Daniel Simões,

When BSC9132 encounters an un-correctable ECC error during NAND boot it stops further booting and asserts HRESET_REQ_B signal. I believe this is what happening in your system and in this case CW may not be able to connect. To boot from NAND with ECC enabled, the data written in NAND should be programmed with proper ECC information.

Thanks,

Yiping

[ds_simoes]

Hi Yiping,
May you clarify the below situation please:

If I set cfg_ifc_ecc[0:1] to 2'b00 (disable), flash the u-boot-nand.bin (with SOR_NAND_ECC_ENC_EN, CSOR_NAND_ECC_DEC_EN, CSOR_NAND_ECC_MODE_4) using the CW-TAP, and then return (cfg_ifc_ecc[0:1]) to 2'b10 (4 bit corretion) and reset the board.

In this case the boot normal occur and the message "WARNING: ECC not checked in SPL, check board cfg" does not appear, what is a good thing, but will the ECC be fully enabled?

Thanks,

Daniel

[yipingwang]

Please configure cfg_ifc_ecc[0:1] to 2'b00, then use CodeWarrior to connect to the target board to erase all the NAND flash.

Then configure cfg_ifc_ecc[0:1]) to 2'b10 (4 bit corretion) and use CodeWarrior to connect to the target board.

Thanks,

Yiping

[ds_simoes]

Hi Yiping,

I followed the process exactly, but it was not yet possible. The logs are slightly different, shown below:

• When I tried to write

fl::target -lc "bblte450_4GFlash_DDR800-core0_RAM_BSC9132PA_Download"
fl::target -b 0x2000 0x30000
fl::target -v off -l on
cmdwin::fl::device -d "MT29F4G08ABADA-IFC" -o "512Mx8x1" -a 0x0 0x1fffffff
cmdwin::fl::device -sd all
cmdwin::fl::device -se 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
cmdwin::fl::erase list
 Beginning Operation ...    
------------------------- 
    log: Using Algorithm: MT29FxG08-IFC.elf 
    log:  
    log:  
    log: ====================================================================== 
    log: === Target Configuration Settings 
    log: === Launch Configuration:       bblte450_4GFlash_DDR800-core0_RAM_BSC9132PA_Download 
    log: ====================================================================== 
    log: Connecting ... 
Performing target initialization ...    
Error:  Connect Failed.
    log: Timestamp:  Mon Oct 21 11:44:10 2019 
Secure debug violation
[CCS last error: Core not responding ](CCSProtocolPlugin)
Error: Connect Failed.‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

• When tried to debug

ccs_open
 ipaddr = 127.0.0.1
 port = 41475
 timeout = 15
 serverh = 0
 ccs_open; ccs_error = 0
ccs_get_connection_count
 serverh = 0
 count = 1
 ccs_get_connection_count; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_available_connections
 serverh = 0
 count = 1
 ccs_available_connections; ccs_error = 0
ccs_cc_version
 serverh = 0
 cc = 0
 version.major = 1
 version.minor = 3
 ccs_cc_version; ccs_error = 0
ccs_set_timeout
 serverh = 0
 timeout = 15
 ccs_set_timeout; ccs_error = 0
ccs_config_server
 serverh = 0
 cc = 0
 server_config = 0
 value = 10230
 ccs_config_server; ccs_error = 0
ccs_get_config_chain
 serverh = 0
 device_list: (size = 0)
 ccs_get_config_chain; ccs_error = 0
ccs_config_chain
 serverh = 0
 cc = 0
 device_list: (size = 1)
  device[0]:: core_type=mpc9132(202)
 ccs_config_chain; ccs_error = 39
 Error message: p1010: Secure debug violation
ccs_get_subcore_error
 serverh = 0
 cc = 0
 error = 57
 chain_pos = 2
 ccs_get_subcore_error; ccs_error = 0; duration=0 ms
ccs_in
 coreh = [serverh:0;cc_index:0;chain_pos:2]
 ccs_io addr: (size = 4)
   0x00000000 0x00035b61 0x00000000 0x00000000
 value: (size = 8)
   01880000 00000200
 ccs_in; ccs_error = 0; duration=0 ms
ccs_out
 coreh = [serverh:0;cc_index:0;chain_pos:2]
 ccs_io addr: (size = 4)
   0x00000000 0x00035b62 0x00000000 0x00000000
 value: (size = 8)
   00000000 00000000
 ccs_out; ccs_error = 0; duration=0 ms
ccs_read_reg
 coreh = [serverh:0;cc_index:0;chain_pos:1]
 index = 30000
 count = 1
 value: (size = 1)
   0x00000ff7
 ccs_read_reg; ccs_error = 0; duration=0 ms
ccs_read_mem
 coreh = [serverh:0;cc_index:0;chain_pos:1]
 addr = [space:0;size:4;address:0xff701010]
 data: (size = 4)
   39000000
 ccs_read_mem; ccs_error = 5; duration=0 ms
 Error message: Core not responding
ccs_close
 serverh = 0
 ccs_close; ccs_error = 0‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

May you suggest other step?

Thank you so much for your support.

Daniel

[yipingwang]

The CCS log is different from the previous, it fails at "ccs_config_chain" to connect to the target board. Please make sure that there is no u-boot on the target board. The error in the CCS log occurs when DDR controller are not initialized correctly.

[ds_simoes]

Hi Yiping,

On CW "Target Tasks" tab, I took an action to erase and checked "Erase All Sectors Using Chip Erase Command" that completed successfully.

Why couldn't the DDR controller are not initialized properly even I'm using the same CW project and u-boot-nand.bin file? With cfg_ifc_ecc[0:1] to 2'b00 (ECC disabled) the process occur correctly.

I don't understand the correlation to know what could be the next step.

Thanks.

Daniel

[yipingwang]

Hello Daniel,

According to the CCS log, CodeWarrior cannot connect to the processor through JTAG when HW ECC enabled.

You have to disable HW ECC when doing flash programming with CodeWarrior.

Thanks,

Yiping

[ds_simoes]

Hi Yiping,

I am a little confused. May be I am not being clear. I need that my Nand works with ECC and that there is the possibility to record the bootloader using the CW with this feature.
Would you know if with HW ECC disabled to write bootloader and after recording enable HW ECC the ECC would work in its entirety?
Best Regards

Daniel

[yipingwang]

You could disable HW ECC to to do NAND flash image programming, then enable HW ECC when setting up u-boot.

[ds_simoes]

Hi Yiping,

I think you are right, but I don't know how I can program the boot-loader in NAND with correct ECC anabled.
Do you know if I need to configure some specific parameter in CW project to burn the bootloader at NAND with proper ECC? 

May you show me the way or indicate a document to clarify this process?

Best Regars,

Daniel