Hello,
I am working on a project with a STM32F412xE controller that uses the SBC UJA1169 for the following purposes: Watchdog, Voltage Supply and CAN communication.
We have managed to setup the SBC, set it in normal mode and configure the watchdog in Timeout and Window mode. CAN communication is also working. So far so good.
The software implemented for the SBC works but now I face the following issue: everytime I need to debug the code (for other reasons, e.g. ADC), the LIMP pin (Fail-safe control register 0x0) is driven low, as the watchdog overflowed. The watchdog is configured in window mode with a timeout of 16ms. This issue only occurrs in debug mode. To me this makes sense, as the software execution is stopped, which leads to the watchdog not being resetted on time and thus overflowing.
I have been reading the Product Data Sheet and at first I thought that setting the chip in the Software Development Mode (SDM) could be an interesting idea, as the watchdog canbe turned off in that mode. But I later realised that in order to do so, the non-volatile memory has to be written. Here I see two issues:
- As described in chapter 7.11.:
If the device has been programmed previously, the factory presets may need to berestored before reprogramming can begin (see Section 7.11.2). When the factory presetshave been restored successfully, a system reset is generated automatically and UJA1169 switches back to Forced Normal mode.
If a reset takes place, I cannot continue debugging in the same session. This is not really useful. - As described in the same chapter:
The MTPNV cells can be reprogrammed a maximum of 200 times
This would mean that I could only debug 100 times: 100 times to set the SDM and 100 times to set it back to normal operation (no SDMC).
I could probably ignore the LIMP pin driven low and continue operation (I´d rather not).
Am I overlooking something about the SBC chip. Did anybody face a similar situation?
Thanks in advance!
