T4241 processor + DDR Issue : Waiting for D_INIT timeout. Memory may not work.

[kumar_086]

Dear Processor Software Experts,

We have a custom-designed board with T4241 processor with DDR memory.

By following similar forum threads reduced the DDR clock frequency using RCW[MEM_PLL_RAT] option, from 8:1 to 5:1. Still the observation is same.

U-Boot log as follows,

U-Boot 2016.012.0+ga9b437f (Jun 11 2021 - 10:37:47 +0530)

CPU0: T4241, Version: 2.0, (0x82400020)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
CPU4:1800 MHz, CPU5:1800 MHz, CPU6:1800 MHz, CPU7:1800 MHz,
CPU8:1800 MHz, CPU9:1800 MHz, CPU10:1800 MHz, CPU11:1800 MHz,
CCB:600 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:150 MHz
FMAN1: 700 MHz
FMAN2: 600 MHz
QMAN: 300 MHz
PME: 466.667 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0c080012 0e12120e 00000000 08000000
00000010: 04360848 30547a00 ec03f000 f9000000
00000020: 00080000 00000000 00000000 0003e000
00000030: 00000000 50000000 00000000 00000038
I2C: ready
Board: T4241, SERDES Reference Clocks:
SERDES1=125MHz SERDES2=125MHz
SERDES3=100MHz SERDES4=100MHz
SPI: ready
DRAM: Initializing DDR

DDR Size: 100000000

Waiting for D_INIT timeout. Memory may not work.

Please help.

[ufedor]

You wrote:

> reduced the DDR clock frequency using RCW[MEM_PLL_RAT] option, from 8:1 to 5:1

This statement contradicts the U-Boot log:

> DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:150 MHz

1) Please doublecheck the SDRAM connection referring the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM.

2) Use CodeWarrior QCVS DDR Validation Tool to check/optimize the DDR controller settings.

[kumar_086]

Dear NXP Team,

We have made a new observation: during this failure case, the DDR CKE pin is not toggling. Attached are the reference oscilloscope images for the same. Please let us know the dependencies of the same. 

Thanks