[T2080RDB] How to configure Common clock for PCIe endpoint

[Venkat_Vellanki]

Hi,

We are working on T2080  PCIe . According to QorIQ_T2080_Reference_Manual(PgNo : 1545) we want to change the Common clock configuration(CCC) bit value in Link Control Register.

Can I get  more information on how to configure it in U-boot level?

Thanks and Regards,

Venkat Vellanki.

[yipingwang]

You can change the link control register in drivers/pci/fsl_pci_init.c

for ex as below to change cc to 1:

pci_lcr = pcie_cap_pos + 0x10;
temp32 |= 0x40;
pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);

[Venkat_Vellanki]

Hi yipingwang  ,

Thanks for the response 

We have already changed as mentioned above but still couldn't configure to common clock.

We configured in the following path /drivers/pci/fsl_pci_init.c

void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
{
#code
if (retrain_link_g)
{
pci_lcr = pcie_cap_pos + 0x10;
temp32 = 0;
pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
printf("pci_lcr: 0x%x\n", temp32);
temp32 |= 0x40;
printf("pci_lcr mk: 0x%x\n", temp32);
pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
udelay(100000);
}
}

Are there any other modifications that are required.?

[yipingwang]

Discussing with the AE team.

[Venkat_Vellanki]

Hi @yipingwang 

Please let us know any update on this as soon as possible .

Thanks,

Venkat Velanki.

[yipingwang]

Please refer to the following update from the AE team.

No further information from software team since it is an old part with old SDK.
customer may search the source code and find a better way on their own.