SPI Initialization problem in SPIMaster_LDD

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SPI Initialization problem in SPIMaster_LDD

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Laartoor
Contributor III

I have set up SPI0 using a SPIMaster_LDD component in Processor Expert ( the version bundled with CW 10.6). In the configuration I have used one chip select signal, an output pin, and disabled the input pin. The code initializes the MCR register:

  /* SPI0_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=1,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */

  SPI0_MCR = SPI_MCR_DCONF(0x00) |

             SPI_MCR_ROOE_MASK |

             SPI_MCR_PCSIS(0x01) |

             SPI_MCR_SMPL_PT(0x00) |

             SPI_MCR_HALT_MASK;        /* Set Configuration register */

  /* SPI0_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=1,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */

  SPI0_MCR = SPI_MCR_MSTR_MASK |

             SPI_MCR_DCONF(0x00) |

             SPI_MCR_ROOE_MASK |

             SPI_MCR_PCSIS(0x01) |

             SPI_MCR_DIS_RXF_MASK |

             SPI_MCR_CLR_TXF_MASK |

             SPI_MCR_CLR_RXF_MASK |

             SPI_MCR_SMPL_PT(0x00) |

             SPI_MCR_HALT_MASK;        /* Set Configuration register */

but then forgets to clear the HALT bit again so that the interface can run.

My code only starts to communicate after I inserted code to clear the HALT bit, before it did nothing.

I use it for a Kinetis K10 processor.

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Petr_H
NXP Employee
NXP Employee

Hi,

Could you please provide more details on how you configured the components ? A sample project .zip file would be the best.

Best regards

Petr Hradsky

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Laartoor
Contributor III

I believe the problem to be in the number of clock configurations for the CPU.

With one configuration, the init code ends like this:

  /* SPI0_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  SPI0_RSER = SPI_RSER_RFDF_RE_MASK;   /* Set DMA Interrupt Request Select and Enable register */

  /* SPI0_MCR: HALT=0 */

  SPI0_MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);

  /* Registration of the device structure */

  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID,DeviceDataPrv);

  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */

And with two clock configurations, the init code ends like this:

  /* SPI0_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  SPI0_RSER = SPI_RSER_RFDF_RE_MASK;   /* Set DMA Interrupt Request Select and Enable register */

  GenMCPIF_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according speed CPU mode */

  /* Registration of the device structure */

  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_GenMCPIF_ID,DeviceDataPrv);

  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */

And SetClockConfiguration only updates CTAR0 without stopping and restarting the module as required by the datasheet ("Do not write to the CTARs while in Running State").

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Petr_H
NXP Employee
NXP Employee

The generated code is influenced by many properties. Please send us the sample project (or at least ProcessorExpert.pe file to reproduce the problem).

Best regards

Petr Hradsky

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Laartoor
Contributor III

This is the PE file with which I can observe the problem

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marek_neuzil
NXP Employee
NXP Employee

Hello,

I have reproduced the problem you has reported. The SPIMaster_LDD generate incorrect initialization code when two and more clock configurations are enable in the CPU component of the project and the SPIMaster_LDD component is enabled in all these configurations (the method HWEnDi is not generated and the HALT bit is not cleared).

As a workaround you can clear the HALT bit in the SPI init funcition. E.g. add the following lines at the end of the init function for SPI0:

/* SPI0_MCR: HALT=0 */ 

SPI0_MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);

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