PE include files set their own DATA_SEG and do not restore to DEFAULT

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PE include files set their own DATA_SEG and do not restore to DEFAULT

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AndersJ
Contributor IV

PE V2.99 for HCS12X

 

It seems that PE include files set their own internal DATA_SEG with

"#pragma DATA_SEG_PrExpxyz_DATA"

 

The same goes for CODE_SEG.

CODE_SEG is restored to DEFAULT at the end of the include file,

which I believe is the correct clean up method

 

DATA_SEG however is not restored to DEFAULT

resulting in my own variables belonging to the PE data segment

and not to the DEFAULT segment which would be a reasonable assumption.

 

Assuming I am correct in my description above I will appreciate answers

from the PE staff, to the following questions:

* Why is the DATA_SEG is NOT restored at the end of the include files?

* Why are PE defined DATA_SEG names not visible in the prm file?

If I am incorrect in my description, please explain where my reasoning is at fault.

 

Thank you,

Anders J

 

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ProcessorExpert
Senior Contributor III

Hello,

 

* Why is the DATA_SEG is NOT restored at the end of the include files?

I think that the pragmas scope ends with end of file. For more details please see 7.2 table in the compiler documentation that is located within the following path: {CodeWarrior}\Help\PDF\Compiler_HC12.pdf

 

* Why are PE defined DATA_SEG names not visible in the prm file?

Pragmas that are generated in the component code are intended to insert whole component code in some specific user memory area and it is user responsibility to create such memory area where the code of the particular component or list of components would be stored. You can create user memory are using appropriate menu command from build options tab.

best regards
Vojtech Filip
Processor Expert Support Team

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AndersJ
Contributor IV

Vojtech,

 

The cut out below is from a *.map file.

The file App_MOG.C has a PE component called "PrExp_DigInpCapture_3" and

a variable Anders J.

AndersJ seems to belong in the PE section.

I would expect it to be in .bss like many other variables.

 

This is the reason I am asking my questions.

Why is the PE section visible inside the code, and why is my variable in that section?

That lead me to believe that PE code is not resetting DATA_SEG to DEFAULT.

The next question is why is this PE section not visible in the *.prm file.

You commented on that as well, but I do not understand what you are saying.

 

Please explain why my variable is in a PE section

 

Thanks,

AJ

 

*********************************************************************************************
OBJECT-ALLOCATION SECTION
     Name               Module                 Addr   hSize   dSize     Ref    Section   RLIB
---------------------------------------------------------------------------------------------

- VARIABLES:
MODULE:                 -- App_MOG.c.o --
- PROCEDURES:
     TestEvery100mS                          FC9979      53      83       2   PAGE_FC_740
     App_MOG_Clock_100mS                     FC99CC       8       8       2   PAGE_FC_740
- VARIABLES:
     STRING.NEXT.1                             CC4A       5       5       1   .rodata1   
     STRING.ENTER.2                            CC4F       6       6       1   .rodata1   
     STRING.BACK.3                             CC55       5       5       1   .rodata1   
     AndersJ                                   2EC5       1       1       1   PrExp_DigInpCapture_3_DATA

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ProcessorExpert
Senior Contributor III

Hello,

 

I don’t understand much to your project structure, so in case you would need more exact answer, please post here some demonstration project.

 

I have created simple project with two Capture components (Cap1,Cap2) that contains Cap1_CntrState and Cap2_CntrState variables and user variable “example”.  I have also divided RAM to two areas by creating MY_RAM section, for details see build options tab. The project is attached.


Unfortunatelly, I haven’t reproduced the problem you have encountered.

Project details:

If you open the map file you can see that Cap2_CntrState belongs to Cap2_DATA_SEG, and Cap1_CntrState variables belongs to Cap1_DATA_SEG. Cap1_CntrState is on 0x3000, Cap2_CntrState is on RAM memory start. The  Cap2_CntrState has no specific PLACEMENT for Cap2_DATA_SEG (for details please see prm file). The Cap2_CntrState variable is placed by linker on beginning of the RAM memory.

best regards
Vojtech Filip
Processor Expert Support Team

 

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AndersJ
Contributor IV

I cannot reproduce it in a small project.

Please contact me off-line and I will send you the entire project with the issue.

AJ

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AndersJ
Contributor IV

Sorry, forgot my email: anders.johansson@fifo.se

AJ

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