Etpu channel has burr when PWM output

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Etpu channel has burr when PWM output

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ZEROOO
Contributor IV

Hi

  When using the ETPU channel to set the PWM output duty cycle to 0 or 100%, there is about 0.19% duty cycle.I would like to know what factors are involved in this phenomenon and whether it is related to the MPC5634 chip itself.

ZEROooo_0-1660011891922.pngZEROooo_1-1660011901413.png

 

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johndiener
Contributor IV

Hello,

Are you using the standard NXP PWM eTPU function?  To update duty cycle are you calling the fs_etpu_pwm_duty() API?  What is your timing configuration - system and eTPU clock frequency, TCR1 counter frequency, etc.?  The standard PWM function is designed to output all the way from 0% to 100% duty cycle, so you should not be getting small pulses if commanding full 0 or 100%. I did a simple test in simulation with the standard PWM function, initializing one instance on a channel and driving 20%, then 100%, 0% and finally 50%, and it worked fine - see below.  But of course there are other potential variables - see questions above.

 

PWM_0_100.png

John Diener

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ZEROOO
Contributor IV

Hi

    I used the following interface :fs_etpu_pwm_init()、fs_etpu_pwm_upate_period、fs_etpu_pwm_upate_duty. CPU = MPC563xM,SYSCLK = 80 MHz,tcr1_freq = 10000000Hz.I can't find the reason for the small pulse. Could you please provide me with a demo?

    

 

 

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johndiener
Contributor IV

Hello,

I downloaded a build of the PWM eTPU function from the ASH WARE eTPU Code Builder and then got it up and running in simulation using your configuration - MPC563xM, 80MHz system, TCR1 at 10MHz.  All looks fine running 0 to 100% duty cycle.  I also downloaded a build from the CodeWarrior eTPU Function Selector and as expected that works the same.

This code:

/* initialize eTPU */
if (my_system_etpu_init())
return 1;

/* start eTPU */
my_system_etpu_start();

/* initialize a PWM output at 20 % duty, 20kHz */
fs_etpu_pwm_init(ETPU_PWM_CHAN, FS_ETPU_PRIORITY_HIGH, 20000, 2000, FS_ETPU_PWM_ACTIVEHIGH, FS_ETPU_TCR1, etpu_a_tcr1_freq);

at_time(1000);
fs_etpu_pwm_duty(ETPU_PWM_CHAN, 10000); /* 100 % , 20 kHz */

at_time(2000);
fs_etpu_pwm_duty(ETPU_PWM_CHAN, 0); /* 0 % , 20 kHz */

at_time(3000);
fs_etpu_pwm_update(ETPU_PWM_CHAN, 10000, 10000, etpu_a_tcr1_freq); /* 100 % , 10 kHz */

at_time(4000);
fs_etpu_pwm_update(ETPU_PWM_CHAN, 10000, 0, etpu_a_tcr1_freq); /* 0 % , 10 kHz */

at_time(5000);
fs_etpu_pwm_update(ETPU_PWM_CHAN, 10000, 5000, etpu_a_tcr1_freq); /* 50 % , 10 kHz */

Produces this output:

PWM_0_100_v2.png

I've attached my project for you to look over - you should be able to use the etpu_gct.[c,h] files and other pertinent source to try it in your setup, or at least check out code differences.

 

John Diener
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johndiener
Contributor IV

Hello,

Are you using the standard NXP PWM eTPU function?  To update duty cycle are you calling the fs_etpu_pwm_duty() API?  What is your timing configuration - system and eTPU clock frequency, TCR1 counter frequency, etc.?  The standard PWM function is designed to output all the way from 0% to 100% duty cycle, so you should not be getting small pulses if commanding full 0 or 100%. I did a simple test in simulation with the standard PWM function, initializing one instance on a channel and driving 20%, then 100%, 0% and finally 50%, and it worked fine - see below.  But of course there are other potential variables - see questions above.

 

PWM_0_100.png

John Diener
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