Ethernet component clock gating bug

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Ethernet component clock gating bug

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PeterFromSweden
Contributor III

Hi

When running init method of ethernet LDD, a hard fault occurs due to missing clock gating of a port.

This can be reproduced easily and a test program is attached.

 

Processor Expert Driver Suite 10.4.1 was used together with IAR 7.30.1.

 

Regards

/Peter

 

  /* THIS WILL FAIL IN ETH1 LINE 231 DUE TO PORT CLOCK NOT SET */

  /* The following two lines fixes it if uncommented */

//  /* SIM_SCGC5: PORTB=1 */

//  SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;

  device = ETH1_Init(NULL);

 

16815_16815.jpgBuild.jpg16816_16816.jpgDebuggerAtError.jpg16817_16817.jpgDebuggerAtInstructionCausingError.jpg

Original Attachment has been moved to: ETH_K64.zip

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4 Replies

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi Peter,

I just import your project to  PE suite 10.4, there are build errors.

do you use Processor Expert Driver Suite 10.4.1 with IAR?

Best Regards,

Zhang Jun

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PeterFromSweden
Contributor III

Yes, I use IAR. Please find further info in updated orignal post.

Regards

/Peter

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marek_neuzil
NXP Employee
NXP Employee

Hi Peter,

I have reproduced the error - there is missing initialization of port clock gate in the Ethernet component. Thank you for reporting this error. It will be fixed in the next release of Processor Expert (update).
You can use the code (you have stated above) in the Ethernet Init() fuction as a workaroud. When you modify the Init() function it is receomended to freze the generated code of the component in the Processor Expert (open the context menu of the Ethernet component in Processor Expert project and select Code Generation - > Don't Write Generated Component Modules).

/* SIM_SCGC5: PORTB=1 */

SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;

Best Regards,

Marek Neuzil

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marek_neuzil
NXP Employee
NXP Employee

Hello,

There is available hot fix of the Ethernet_LDD component, see the attached file.

Best Regards,

Marek Neuzil

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