[MC33931 Japan] MC33931 D1 pull-up

[JozefKozon]

Hi Team,

could you please answer customers questions? In the datasheet it is confirmed, that the D1 has pull-up resistor, but it is not stated where is the D1 pull-up supplied from. Is it VDD? 

DESCRIPTION

I think that the D1 terminal has a built-in internal pull-up.
Could you tell us about this internal pull-up?

Is this pull-up voltage supplied by Logic VDD?
Could you please tell me the typ / min / max of this voltage?

The IIN current value in the data sheet is recognized as the value under the condition of 5 to 28V for VPWR. Is this correct?

With Best Regards,

Jozef

[Wayne_Anderson · Accepted solution]

Hello,

The D1 pin is a Schmitt trigger input with ~80ua source so default condition is pull high to disable outputs OUT1 and OUT2. D1 pin Minimum input logic threshold high = 2.0V. Maximum input logic threshold low = 1.0V.

The pull-up voltage is supplied from VPWR via internal charge pump. Charge pump voltage Vcp is min 3.5V to max 12V, typical 5V.

The IIN value in the data sheet is specified with VPWR = 5.0V; VPWR operating voltage range is 5.0V to 28V.

Wayne

[Wayne_Anderson]

Correction: D1 pull-up voltage is referenced the internal logic level LDO which is VDD.

[JozefKozon]

Hello Wayne, 

thank you for your answer. I have posted it to the customer and he has sent me a reply with some additional questions. Could you please provide answers? Please see below and an excel file attached.

DESCRIPTION

Thank you for your support.

I have received an additional inquiry regarding the answer you provided.

I have included the additional inquiry in the excel.

I would appreciate it if you could check again.

They need to finish evaluating a prototype board to be provided to an OEM by the end of this week,

and their request is for an answer as soon as possible.

With Best Regards,

Jozef

[Wayne_Anderson]

Hi,

Correction to previous statement. I double checked this with a colleague. He confirmed that the D1 pull-up is referenced to an internal logic level LDO which is VDD. That is why operating input voltage is stated as 5.5V maximum. Therefore, there should be no difference in the IIN input logic currents between VPWR at 5V and VPWR at 16V. The block diagram in the data-sheet is somewhat mis-leading in this regard.

[JozefKozon]

Hi Wayne,

thank you for the correction. I have sent it to the customer and he has just sent me a reply. Please see below.

DESCRIPTION

Thank you for your quick response.

I understand. The pull-up of D1 is VDD, isn't it?

I apologize for the inquiries made many times, but it would be helpful if you could tell us the output voltage range of VDD(min,typ,max).

I couldn't find it in the data sheet.

Also, I think that VDD is generated via VPWR, but if VDD is typ 5V, there are the following concerns.

When VPWR = 5V, which is the condition of "IIN", the internal VDD voltage is considered to be lower than 5V at the dropdown of the LDO.

Therefore, I would like to know the pull-up voltage value (VDD) under the condition of VPWR = 5V (IIN).

Also, I would like to know how much the IIN changes under the condition of VPWR = 16V (customer use condition).

Would you please check again?

With Best Regards,

Jozef

[Wayne_Anderson]

DESCRIPTION

Thank you for your quick response.

I understand. The pull-up of D1 is VDD, isn't it? Yes, Internal LDO VDD 5V.

I apologize for the inquiries made many times, but it would be helpful if you could tell us the output voltage range of VDD(min,typ,max).

I couldn't find it in the data sheet.

There is no data sheet information for VDD min, max. Typical output will be 5V as this is an internal logic level LDO 5V. 

Also, I think that VDD is generated via VPWR, but if VDD is typ 5V, there are the following concerns.

When VPWR = 5V, which is the condition of "IIN", the internal VDD voltage is considered to be lower than 5V at the dropdown of the LDO. As long as the VPWR is >=5V the internal LDO will maintain 5V VDD.

Therefore, I would like to know the pull-up voltage value (VDD) under the condition of VPWR = 5V (IIN).

Lab results using evaluation board indicate ~4.25V pull-up level on D1 pin when VPWR=16V, and ~4.12V pull-up level on D1 pin when VPWR=5V. There is an internal diode in series with the internal pull-up resistor which results in the diode voltage drop in this D1 input pull-up level.

Also, I would like to know how much the IIN changes under the condition of VPWR = 16V (customer use condition).

No additional information on logic input currents outside of what is specified in the data sheet. With internal pull-up to LDO VDD there should be very little difference with VPWR=16V.