ucc switching between fast protocols and slow protocols is not working

[amanagantivinod]

Hi All,

We are working on MPC8309 processor, we are using the ucc-5 for synchronus-HDLC and Asynchronous-UART purpose. Here UCC is configured in fast protocol mode for HDLC and slow protocol for UART mode.

We have verified the UCC  for UART and HDLC mode both are working fine, but whenever we are switching the UCC from fast protocol [HDLC] to slow protocol [UART] UCC is not workking.

We tried the protocol switching sequence mentioned in the QE reference manual, but it did not help. but whenever we issue a QE-RESET then from fast protocols to slow protocol switching is working.

But we should not issue a QE-reset command as other UCC ports are used for some other purpose and should not be disturbed.

We are observing below things.

1. when switching from slow protocols to fast protocols UCC is working fine in HDLC mode without  any issues

2. Whenever switching from fast protocols to slow protocols UCC_UART_UCCE_BSY interrupt is triggered and ucc stopped working, we tried re-configuring transmitter and receiver for BSY error interrupt, but still it did not help.

We are using the standard platform drivers provided by NXP for HDLC and UART, could you please suggest the exact flow that should be followed for switching from fast protocols to slow protocols, 

Your help is appreciated in  advance. it would be  great, if sample test code is provided for this switching which indicates the exact sequence.

[sujay1]

Hi,

Can you tell me where you added this code snippet? was it in ucc.c or ucc_slow.c?

[Pavel]

The following command sequence is recommended:

To switch a UCC’s protocol without resetting the board or affecting other UCCs, follow these steps:

1. Clear GUMR_L[ENT, ENR].
2. If a protocol switch is preformed from fast protocol: Issue the Pushsched host command for UCC Transmitter (CECDR value 0x80). Issue the Pushsched host command for UCC Receiver (CECDR value 0x82).
3. Make protocol changes in the GUMR and additional parameters then issue the INIT TX and RX PARAMETERS command to initialize both Tx and Rx parameters.
4. Set GUMR_L[ENT, ENR] to enable the UCC with the new protocol.

See the Section 6.8.5 of the QUICC Engine Block Reference Manual with Protocol Interworking:

https://www.nxp.com/webapp/Download?colCode=QEIWRM&Parent_nodeId=1281540457516714915076&Parent_pageT...

Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[amanagantivinod]

Hi Pavel,

Thanks for your reply, We have tried the sequence that you mentioned..

Please find the snippet of the code,  let me know if anything is wrong in the sequence..

    /* Set UCC to slow type */

    ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);

    ucc_slow_disable(uccs, COMM_DIR_RX_AND_TX);

    id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);

    ret = qe_issue_cmd(0x0F, id,

             QE_CR_PROTOCOL_UNSPECIFIED, 0X80); //FOR TRANSMITTER (0xF is PUSHSCHED command)

    ret = qe_issue_cmd(0X0F, id,

             QE_CR_PROTOCOL_UNSPECIFIED, 0X82); //FOR RECEIVER (0xF is PUSHSCHED command)

Followed by rest of initialization of PRAM, Buffer descriptors, etc then INIT_TX and INIT_RX commands issued after that Enabled the Tx and Rx sections of the UCC.

Could you please let us know why the BSY interrupt is  triggered while switching from fast protocol mode to slow protocol mode?

Your help is appreciated in advance.

[amanagantivinod]

Hi Pavel,

Thanks for your reply, We have tried the sequence that you mentioned..

Please find the snippet of the code, let me know if anything is wrong in

the sequence..

id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);

/* Set UCC to slow type */

ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);

if (ret) {

printk(KERN_ERR "%s: cannot set UCC type", __func__);

ucc_slow_free(uccs);

return ret;

}

ucc_slow_disable(uccs, COMM_DIR_RX_AND_TX);

ret = qe_issue_cmd(0x0F, id,

QE_CR_PROTOCOL_UNSPECIFIED, 0X80); //FOR TRANSMITTER (0xF is

PUSHSCHED command)

if(!ret){

printk("