Timeout error while waiting for FLG bit in CPCR register to be cleared

[rvijay435]

The issue is related to the timeout error while waiting for the Communications Processor to clear the FLG bit in CPCR register (CP Command Register).

The operation is when the FLG bit is set, we cannot give another command. Only when the CP clears the FLG bit set by Core, we can give other commands.

The SCCx (where x is from 1 to 4) for UARTs is configured as per section 21.21 in the MPC8280 Reference Manual. We are waiting on the CPCR FLG bit to be cleared for 6 SECONDS. But we still
see the timeout and the FLG bit is not cleared by Communications Processor.

Reference: MPC8280RM which can be found in http://www.nxp.com/docs/en/reference-manual/MPC8280RM.pdf.

[alexander_yakov]

Before sending any command to CPCR register please perform the following.

1. Clear entire DPRAM by filling it by zeros

2. Issue "reset" command by setting CPCR[RST] along with CPCR[FLG] flag.

3. Wait for FLG bit cleared.

After this procedure you can begin initialization of CPM peripherals and issue commands to CPCR.

Have a great day,
Alexander
TIC

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[rvijay435]

Hi Alexander,

Thanks for the response.

And one more doubt, is there any specific time I have to wait fro FLG bit to be cleared??? Like few milli-seconds?

Thanks in advance.

[alexander_yakov]

Our documentation does not specify this time, but yes, it should be significantly less than mentioned 6 seconds.

[rvijay435]

Sure.

Thanks Alexander.