T1022: D_INIT timeout Memory may not work

[hemwant]

We are having a customized board with T1022 processor , which has SPI flash connected to the processor (SPI CS0) and we are trying to boot our uboot from SPI flash. The APACER DDR4 MINI is used in the card and part number of the same is 75.B93GK.G000B. The SPI flash gets successfully programmed using lauterbach tool.

The uboot gets struck at D_INIT Timeout. The uboot logs with DDR SPD debug logs enabled is attached below. I am also attaching lauterbach(t32) DDR section register dumps.

The RCW used is as follows-

# serdes protocol 0x87
0C10000E 0E000000 00000000 00000000
87000000 00400112 EC110000 21000000
00000000 00000000 00000000 0003A000
00000000 84160A05 00000000 00000000

Initializing....using SPD

0 : 23 info_size_crc bytes written into serial memory, CRC coverage
1 : 11 spd_rev SPD Revision
2 : 0c mem_type Key Byte / DRAM Device Type
3 : 06 module_type Key Byte / Module Type
4 : 84 density_banks SDRAM Density and Banks
5 : 19 addressing SDRAM Addressing
6 : 00 package_type Package type
7 : 08 opt_feature Optional features
8 : 00 thermal_ref Thermal and Refresh options
9 : 60 oth_opt_features Other SDRAM optional features
10 : 00 res_10 Reserved
11 : 03 module_vdd Module Nominal Voltage, VDD
12 : 01 organization Module Organization
13 : 0b bus_width Module Memory Bus Width
14 : 80 therm_sensor Module Thermal Sensor
15 : 00 ext_type Extended module type
16 : 00 res_16 Reserved
17 : 00 timebases MTb and FTB
18 : 0a tck_min tCKAVGmin
19 : 0c tck_max TCKAVGmax
20 : 1c caslat_b1 CAS latencies, 1st byte
21 : 00 caslat_b2 CAS latencies, 2nd byte
22 : 00 caslat_b3 CAS latencies, 3rd byte
23 : 00 caslat_b4 CAS latencies, 4th byte
24 : 6e taa_min Min CAS Latency Time
25 : 6e trcd_min Min RAS# to CAS# Delay Time
26 : 6e trp_min Min Row Precharge Delay Time
27 : 11 tras_trc_ext Upper Nibbles for tRAS and tRC
28 : 18 tras_min_lsb tRASmin, lsb
29 : 86 trc_min_lsb tRCmin, lsb
30 : 20 trfc1_min_lsb Min Refresh Recovery Delay Time, LSB
31 : 08 trfc1_min_msb Min Refresh Recovery Delay Time, MSB
32 : 00 trfc2_min_lsb Min Refresh Recovery Delay Time, LSB
33 : 05 trfc2_min_msb Min Refresh Recovery Delay Time, MSB
34 : 70 trfc4_min_lsb Min Refresh Recovery Delay Time, LSB
35 : 03 trfc4_min_msb Min Refresh Recovery Delay Time, MSB
36 : 00 tfaw_msb Upper Nibble for tFAW
37 : c8 tfaw_min tFAW, lsb
38 : 28 trrds_min tRRD_Smin, MTB
39 : 30 trrdl_min tRRD_Lmin, MTB
40 : 32 tccdl_min tCCS_Lmin, MTB
41 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60 - 77: 04 23 0c 36 0e 2e 16 2c 0e 2e 16 2b 0d 2e 15 2c 03 24 mapping[] Connector to SDRAM bit map
117 : 00 fine_tccdl_min Fine offset for tCCD_Lmin
118 : 00 fine_trrdl_min Fine offset for tRRD_Lmin
119 : 00 fine_trrds_min Fine offset for tRRD_Smin
120 : 00 fine_trc_min Fine offset for tRCmin
121 : 00 fine_trp_min Fine offset for tRPmin
122 : 00 fine_trcd_min Fine offset for tRCDmin
123 : 00 fine_taa_min Fine offset for tAAmin
124 : 00 fine_tck_max Fine offset for tCKAVGmax
125 : 00 fine_tck_min Fine offset for tCKAVGmin
126-127: f2 16 SPD CRC
128-255: 11113f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003fc6320 : 01 Module MfgID Code LSB - JEP-106
321 : 7a Module MfgID Code MSB - JEP-106
322 : 10 Mfg Location
323-324: 19 05 Mfg Date
325-328: 06 21 90 54 Module Serial Number
329-348: 44 33 31 2e 32 35 31 38 30 53 2e 30 30 31 20 20 20 20 20 20 Mfg's Module Part Number
349 : 00 Module Revision code
350 : 80 DRAM MfgID Code LSB - JEP-106
351 : ce DRAM MfgID Code MSB - JEP-106
352 : 00 DRAM stepping
353-381: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Mfg's Specific Data
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
Waiting for D_INIT timeout. Memory may not work.
2 GiB left unmapped

Loading second stage boot loader

[hemwant · Accepted solution]

In our case there were assembly issues between PCB and DDR connector. On soldering the same DDR got initialized properly and uboot booted up.

[hemwant]

We have received our DDRv tool for DDR validation . Could please share the link of latest code warrior tap software and its installation guide.

[Bulat]

Latest CodeWarrior software can  be found here:

https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=7360207

[Bulat]

Wide range of issues can cause your problem. Did you try to run DDRv tool for DDR validation? This can help to clarify if the problem happens within u-boot code or not.

What is strange among setup of DDR controller is values of DDR_SDRAM_MODE_9 and DDR_SDRAM_MODE_10 registers. These two should not be 0x0 after u-boot.

Regards,

Bulat

[hemwant]

@Bulat    thanks for the suggestions.

We haven't tried DDRv tool for DDR validation for now. We are arranging the same . Is there any document regarding the possible causes of D_INIT timeout ? We can refer the same in meantime.

We are having other customized boards with T1022 processor, DDR controller values of DDR_SDRAM_MODE_9 and DDR_SDRAM_MODE_10 registers is 0x0 in those boards as well and they are properly booting up with the same DDR part code.

[Bulat]

D_INIT timeout means that DDR controller was not able to initialize the SDRAM during automatic calibration procedures. As I wrote, a wide range of issues can cause this problem. This includes incorrect schematics, incorrect layout, board level issues (like bad soldering, defects of PCB/components), incorrect DDR settings, incorrect DDR clock frequency, bad power supplies.

DDR_SDRAM_MODE_9 and DDR_SDRAM_MODE_10 registers registers define settings of SDRAM Mode Registers 4, 5 and 6 (MR4, MR5, MR6). Some bits of MR5 and MR6 must be set as per SDRAM's data sheet. For example, MR5[10]=1 enables Data Mask signal (DM), MR6[12:10] must be set to 001 for data rate of 1600MT/s. Normally u-boot automatically sets these bits, that is why I called this "strange".

Regards,

Bulat