Question about a MPC8270 processor in PowerQuicc II series

[han-jinjang]

The reference figure on datasheet, MPC8272EC/Rev.3/figure 6, shows that the data is doing a transit at rising edge and is sampled at falling edge.
But the result of our experiment seems that the RX data sampling was performed at rising edge.

My system is configured to followings;
 1) MPC8270, SCC, HDLC, NRZ coding
 2) Receive Data sampling using internal clock

Requests;
 1) Default RX sampling edge when SCC uses a internal clock
 2) Concrete method to select a RX sampling edge
    On datasheet, It seems that a sampling edge with respect to RX data can be arbitrarily changed

I hope your solutions sincerely.

Thank you

handoojin@hanmail.net

[alexander_yakov]

SCC in NMSI HDLC mode samples input data on falling edge and this is not configurable.

For transmit side output data is driven on rising or falling edge, this is configurable by GSMR_L[TCI].

Have a great day,
Alexander
TIC

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