PCIe reset to Root Complex and End Point device

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PCIe reset to Root Complex and End Point device

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Contributor III

Hi,

    We have a proto design based on MPC8569E.

    A PCIe End Point(EP) device is connected to Processor (PCIe Root Complex). The EP device correctly gets enumerated on PCIe bus on power-up of the target.

The question is, does this EP device will get enumerated again on PCIe bus, if only the PCIe root complex (Processor) is given reset.

Regards

Ram

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NXP TechSupport
NXP TechSupport

Yes, EP will be discovered and enumerated correctly in the described case.

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Contributor III

Hi, 

    In our case the EP device is not getting enumerated on PCI bus in the case when only the Root complex(Processor) is given reset.

What could be the possible reason? What are the areas to look into for debugging ?

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NXP TechSupport
NXP TechSupport

How exactly reset is applied to the processor?

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Contributor III
Hi
The following sequence is used for processor reset
1) Processor is in functioning state. Its HRESET is controlled by CPLD.
2) An external button is sensed by CPLD which initiates a power on reset cycle on the HRESET pin of processor.
3) The timings are similar as described in the reference manual. It is same as when we power up the card in which PCIe end point is enumerated
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NXP TechSupport
NXP TechSupport

Is the EP direcly connected to the processor?

What is the value of the PCIe controller LTSSM State Status Register—0x404 in case of failure?

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Contributor III

Yes , EP is directly connected to processor and is capacitevely coupled.

>>What is the value of the PCIe controller LTSSM State Status Register—0x404 in case of failure?

I will share the results soon.

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Contributor III

>>What is the value of the PCIe controller LTSSM State Status Register—0x404 in case of failure?

The value of LTSSM is 0x06 in case of failure.

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NXP TechSupport
NXP TechSupport

The LTSSM value means that the PCIe interface can’t proceed on link training.

At least one lane previously detected a receiver doesn’t send correct TS1 or TS2 training sequence.

This means that EP device does not enter link training state in the discussed case.

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Contributor III

The issue is still unresolved from our end.

Please suggest what should we look for to debug this issue.

Is it in the software or lies with the hardware ?

Regards

Ram

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NXP TechSupport
NXP TechSupport

As I wrote in the previous response:

> This means that EP device does not enter link training state in the discussed case.

The issue could be resolved by applying reset signal to the EP.

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Contributor III

Thanks for your reply.

    

>>The issue could be resolved by applying reset signal to the EP.

That is precisely we don't want to do, as this device is in data path which should not be disturbed. We want this EP to be re-enumerated when only the ROOT Complex(Process) comes up again after soft reset.

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Contributor III

Can you suggest any PCIe registers in the root complex(Processor) side that may reflect the status or error condition. This could be the clue for further debugging.

If you have any other debugging suggestions please share.

Please suggest.

Regards

Ram

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NXP TechSupport
NXP TechSupport

The issue is caused by the endpoint device - i.e. nothing has to be debugged at the processor's side.