P1021rdb gets hung in using 1588 timer for finding external clock frequency

[amanagantivinod]

Hi All,

We are using P1021rdb in our project and need to calculate external clock frequency coming from V.35 interface, We are using IEEE1588 timer for this purpose.

1) Connected V.35 clock to 1588 timer clock input clock pin

2) We have remapped the eTSEC1 timer module memory space

3) Configured the timer control register, to select the external clock as clock input source, and set BYP bit to Bypass drift compensated clock

4) Now reading counter value every 100ms (soft timer is used to get triggersat every 100ms) taking average of values collected for 20 times

5) We are able to read the clock frequency properly

Problem:

If the external clock is disconnected at run time then system is hanging, when we connect it back then system is resuming its execution..

Could you please let us know where we are doing wrong, it would be great if you can share sample code to find out external clock frequency using 1588 timer.. :smileyhappy:

[bpe]

Did yo try to debug your code with a JTAG debugger? What exactly happens with the processor when it "hangs"?

Have a great day,
Platon

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[amanagantivinod]

Hi platon,

Thank you for your support,

We don't have any JTAG debugger as of now, could you please let us know in

which scenarios it can happen like this and only happening for this

specific piece of code.

Please find the attached file, which has simpler functions to find out

clock rate, please let us know anywhere we are doing wrong..

[bpe]

The way you use the timer is not safe. The main purpose of IEEE1588

dedicated timer is to generate a  network-synchronized clock for the

rest of the system. To achieve this, the reference clock fed to the

timer input _must_ be  stable and continuous. The documentation  does

not specify the behaviour of  the device if the external reference

clock stops.  Moreover, the chip hardware  specification limits the

frequency range for this clock. No correct operation is guaranteed

if these requirements are not met.

Have a great day,
Platon

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[amanagantivinod]

Hi platon,

Thanks for your reply and sorry for the delay, I was stuck due to other high priority issues.

We are not using this 1588 timer for Ethernet controller section.

As per P1021 reference manual ( page no. 1056 ) there is a register called ,Time stamp status register * (eTSEC1x_TMR_STAT). Which has RCD bit to indicate input clock presence.

But this bit is not updating as per the input line status, I mean once the bit is set to 1, after clock detection, its not updating to zero if we remove the cable. its going to zero if we give a soft reset to the timer, could you please let me know, why Status register is not updated based input clock state.