MPC885 reset problem

[chiranjeevimadd]

Hi,

     In MPC885 we are facing problem with reset. When we power on the board for first time, the processor will execute boot code continously and will not get into the system code. when we power off and power on next time, it will execute. We are not getting any reason for this behaviour.

[chiranjeevimadd · Accepted solution]

HI

     Thanks to every one who helped me for resolving the issue. Actually, the problem is not in SDRAM, but with SDRAM initialization. The UPM RAM words which are used to configure the SDRAM are corrupted when the board is not working, so the TEA is generated. When the UPM RAM words are configured correct in processor, problem does not occurs.

     So, we reconfigured the UPM RAM when we came into main function, but not activated the SDRAM chip select until then. We used DPRAM for both RAM and stack memories.

[srikanthgedigam]

hi ....

did u understood the point.......

I know that, if power pc mpc885 for long time without reset, the bga gets heated up........

may it's functionality gets damaged.

But, u can try this using fpga from one board and processor as another board....so that it gets confirm.

Hope QorIQ processor.......going well.............DDR2/DDR3 any issues......in understanding.

Regards,

Srikanth.

[srikanthgedigam]

hi....

i think fpga , here using is XC6SLX150/45, here the prom being connected in spi mode......i am sure abt this.

As per ur answer, the prom takes loading 2min i.e., 120sec........

i think it wont takes more then 18sec.......i know that......

or else u do one thing......for testing purpose......u can take FEC board or any other board for spare pin

then use for 20us duration......

try this.....make it sure.....initally whehter it is working or not.

Regards,

Srikanth.

[chiranjeevimadd]

Hi...

     So, you are saying me to hold the reset of the processor until the fpga gets loaded from PROM. If so, it cannot be done because loading of fpga takes 2 min appr. so, processor cannot be put in reset till it is loaded.

[srikanthgedigam]

Hi.........

Is their any issues with the new layout version .........board with any Problems?

Hopefully..........reset issue resolved.................still issue going on............

Regards,

Srikanth.

[srikanthgedigam]

hello.........

if ur suspecting the reset issue........just elimnate the reset ic........after power on.......give reset duration from fpga........

In Brief

At damping resistor of the reset ic, left with pin of reset ic of sp706/max 706.

Now connect any one the fpga spare pin to the damping resistor........at reset side.

Ask ur collegue, to write the code in fpga like this, intial after power on......high, then low for 20us, then high always.

If it works,......then issue is reset..........

Work on this.........it is solved by this observation......i will give u final solution.....how to resolve with reset ic.

Work out...................

Regards,

Srikanth.

[lunminliang]

What do you mean by "boot code" and "system code", what is the exact (hardware) difference between these two codes, and also describ what happens when it "not get into the system code" - what happens in this case exactly (in terms of hardware), if the device stops or reboots somewhere, then what is the last instruction executed before stop(or reboot), and what this instruction is exactly doing (or intended to do).

[chiranjeevimadd]

We are using SDRAM only, not DDR. In the boot code it will execute, reset, reset@rom and user init functions and it will not jump into main function. when we restart the power supply, it will execute fine into system code.

[genuap]

Sorry - SDRAM. So, are you able to figure out where it stalls? It sounds like it is very far from getting to to the jump to SDRAM, correct? (you're main is probably in flash)

What if you just toggle HRESET and don't restart the power supply? (by the way how is POR reset generated?)

Based on your comment with the power supply I would look at four things:

1) double check the Power on Reset resistor straps - make sure you have them for every pin. Be careful if you're using a bus hold latch in there for the POR resistor straps too.

2) Check the clock - is the clock there and stable when the reset goes away.

3) make sure you have pullups on POR, HRESET. SRESET

4) And look over the power sequencing - make sure all of the supplies are coming up at the same time.

[chiranjeevimadd]

We had already send the hardware related sch,bom to freescale technical team. As per their  verification  hardware is ok.

one observation  is with fast on/off   it is working ,but with slow on/off it is not working( stoped  with in  the init.c  . this we observed in rom version debug mode).what might be problem.

[hwrobel]

Regarding spurious startup issues on PowerQUICC I, I recommend to check all pull-ups and downs(!) on the JTAG/BDM port (TRS/TMS/DSCK etc) and make sure that they are 1k instead of 4k7. I have seen board layouts and configurations where 1k was required.

As per other posts, it is unwise to keep the part powered up without asserting reset.

Hope this helps.

[chiranjeevimadd]

If it is so, in problem condition  processor sholud not up , but here  in problem case processor flash code is executing up to some extent in init.c.When executing data section copy from flash  to sdram it is pointing to unknown location.  Individually if we test flash and sdram they  are  ok. board is working 5 times,if  we do power on/off  10 times

[chiranjeevimadd]

one more observation is in problem condition TEA is generating and sdram & flash chip selects coming simultaneously.

for gpcm ( flash) TA is disabled. SDRAM is connected to UPMB and its wait mode disabled.

[genuap]

Do you have any idea how much code it's executing?

A common point of failure would be when it jumps from executing from flash to executing from DDR. Did you verify if the DDR works? Easiest way to do that is through an emulator - connect up and use the emulator to configure and access the DDR.