MPC8347 GPCM with DLL Bypass Local Bus Timing

[jonbonte]

I have a couple questions.

1. When looking at the MPC8347EA Power QUICC Hardware Specifications (Revision 12), I notice that when the local bus is in GPCM & DLL Bypass mode, all of the timing parameters are in reference to the falling edge of LCLK.  However, in the MPC8349EA Power QUICC Family Reference Manual, diagrams seem to to show local bus transactions as if they were in relation to the rising edge of the clock.  For example, look at Figure 10-29 on page 476 of the reference manual.
   • Are the diagrams in the reference manual assuming that the DLL is enabled?  So, if the DLL was bypassed, figure 10-29 would have transitions on the falling edge of the clock instead of the rising edge (LAD changes from address to data)?
2. The Hardware Specifications Figure 22 for Local Bus signals in DLL Bypass mode only shows tLBKHOZ (Local bus clock to output high impedance for LAD/LDP).  However, if you look at diagrams in the reference manual, LAD is transitioning directly from Address to Data.   Is there a clock cycle of Hi-Z inbetween address and data output, or does the LAD bus transition directly from Address to data?  If so, how do I reconcile this with tLBKHOZ?  Could I instead use tLBKLOV on the next cycle to determine when the Address transitions to data?
3. Lastly,  I could not find any location in the reference manual that defines when LWE is asserted (it says when it is negated).  My best guess is going from Figure 10-29, it seems like LWE is asserted for...

LWE_duration = SCY + TRLX + 1 -(1/4*CSNT);

[jonbonte]

One more question.

4. During which clock cycle is the read data on LAD actually sampled when using a GPCM mode bus.  For example, I have a GPCM Read configured with TRLX=0, EHTR=0, XACS=1, ACS=11, LCRR[CLKDIV] =4 with LALE asserted for 4 cycles and SCY=6.    As such, my LOE assertion and read data last longer then the one cycle shown in figure 10-24 of the CPU reference manual.

Right now, I am assuming that LAD is sampled the clock cycle before LOE is negated (the last cycle it would be asserted).  It would be nice to get some confirmation on that, as that information is not clear from the reference manual.  The CPU hardware specification gives setup and hold times in relation to an edge, but I do not know which edge to look at.

[alexander_yakov]

The LBC controller acts as "target" device on internal bus. Bus transaction is always terminated by internal "transfer acknowledge", which is in case of LBC generated by LBC. Reference Manual shows this internal signal as TA on LBC-related figures. Internal bus samples data on the cycle, on which TA is asserted.

The following is said in Section 10.4.1.3 "Data Transfer Acknowledge (TA)":

The three memory controllers in the LBC generate an internal transfer acknowledge signal, TA, to allow

data on LAD[0:31] to be either sampled (for reads) or changed (on writes). The data sampling/data change

always occurs at the end of the bus cycle in which the LBC asserts TA internally.

Typically, this cycle with TA asserted at the last cycle of LBC access.

[alexander_yakov · Accepted solution]

1. Yes, Reference Manual shows clock polarity as for "DLL enabled" mode. For DLL bypass please use clock for scale purpose only, actual signal assertions/negations timing and reference edge is shown in Figure 22 of Hardware Specifications.

2. No, there is no gap between address and data, LAD will transittion directly from address to data, and data will be valid with tLBKLOV timing parameter.

3. LWE is asserted on the next cycle immediately following LCS assertion, as shown at Figures 10-25 and 10-27, negation is controllable by several timing parametres, see Table 10-23 for LWE negation timing.

Have a great day,
Alexander

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