Make sure the least significant bit (bit 31) of the configuration word address is CLEAR to signify addresses.
> local access window is enabled for DDR SDRAM controller.
Can you initialise the DDR controller using this mechanism? I thought you'd need to do that from code loaded into SRAM.
It might be easier to load code into SRAM that configures the peripherals and DDR and then have it load the main code. Except this CPU doesn't have internal SRAM, does it?
Does Freescale provide any working examples with the development board or elsewhere?
Could this be relevant?
>> 4.3.3.2.3 EEPROM Data Format in Reset Configuration Mode
>> IMMRBAR value is prepended to the EEPROM address to generate the complete
>> memory-mapped register’s address.
You shouldn't attach huge Reference Manuals or Data Sheets to your posts. That's a waste of space. We know where to get these from anyway. Just post LINKS to the documents on Freescale's web site instead.
Tom