MPC8260A(Hip4) startup problem?

[mengjunling]

Hi:

Now I buy MPC8260ACZUMHBB chips from RS,  and assembly on my board.

I read the PVR and IMMR, the values indicates Hip4 revision, the package marking (4K25A QQDK1036 MALAYSIA) is identical to PVR/IMMR.

Now I have a new problem, when I power up my board, the UART(from SMC1) can't output anything, but keep powering on after about several minutes, I reset my board or recycle the power,

UART can output correctly, I don't know why?

But another board assembled MPC8260(Hip3) device boots correctly everytime, and the only difference between two board is different CPU revisions(one is Hip3, another is Hip4).

In my design I don't control the power sequence,VDD_Core(1.8V) and VDDH(3.3V) power up at the same time, but the VDD_Core powers quickly,

In AN2290, I find the following states, I want to know if the power sequence affect the MPC8260 boot and cause my problem?

2.3 Power Sequencing

One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp

up at different rates. The rates depend on the nature of the power supply, the type of load on each power

supply, and the manner in which different voltages are derived. The following restrictions apply:

• VDD/VCCSYN—Must not exceed VDDH by more than 0.4 V at any time, including during

power-on reset.

• VDDH—Can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 msec.

During normal operation, should not exceed VDD/VCCSYN by more than 2.0 V (HiP3) or 2.5V

(HiP4).

• VIN—Must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

I

On my board, the spare pins U5, V4, and AE11 (on PCI devices, AE11 is CLKIN2) is grouded.

and the AF25(PCI_MODE#) pin is pulled up. XFC pin capacitor is 1200pF.  Clocking setting is 200/133/66Mhz(0101_111, Local mode), clock input is 66Mhz

The Local bus interface is not used, so I left it floating, only fewer pins is connected.

[alexander_yakov]

Sorry, we need to look your schematic to debug this problem. Please create a Service Request to Freescale Online Technical support and attach your schematic to Service Request.

New Service Request

Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[mengjunling]

Now I set the SMC in Loopback mode to exclude the affects of external MAX3232,. After power-up, the SMC still can't generate interrupt.

In MPC8260UM, Table 27-2 describe SMC parameter RAM,

"Note 2 Not accessed for normal operation. May hold helpful information for experienced users and for debugging." And how can I get detailed internal state information?

I compared the parameter RAM between Hip3 and Hip4 devices, and found some differences at offset 0x14/0x18.

[mengjunling]

In MPC8260ACE,

G3. PLL does not lock on the rising edge of the input clock CLKIN

In correct operation, the PLL of the MPC826x devices will lock on the rising edge of the input clock.

However, on the MPC826xA (Hip4) silicon, the PLL locks on the falling edge of the input clock if an integer

CPM multiplication factor is used. This will affect the skew between CLKIN and internal clock at the rising

edge since the skew is dependent on the duty cycle of the input clock. This will affect synchronous designs

where the same clock source is used as an input to CLKIN as well as to an external synchronous device (e.g.

a peripheral or ASIC). The MPC826xA internal logic assumes that the internal clocks rising edge will be in

sync with CLKIN.

Workaround: Use a non-integer CPM multiplication factor. This workaround does not apply to PCI agent

mode, since the multiplication factor in PCI agent mode must be an integer.

My clock setting is 200/133/66Mhz, MF =2 ,  so the main PLL locks on the falling edge of CLKIN, but the FPGA on my board is a 60x Slave and use the same clock source with CLKIN by a clock buffer(CY2309). Does this affect the CPU startup?

[mengjunling]

I have created a new SR, and attached my schematic for you. Please help me to fix the problem.

Thanks