MPC8250 timing issue with SDRAM

[johnman]

Hi,

I meet a problem regarding the timing between MPC8250 and SDRAM.

The data retention period(after rising clock edge to data invalid) from MPC8250 is 0.5ns min. (SP30), However, SDRAM requires hold time after rising edge 0.8ns (tAH or tDH). 

But in MPC8250 datasheet, it says it can achieve glueless interface to SDRAM memory. Could you help to explain how MPC8250 can mitigate this timing gap?

Thanks

John 

[johnman]

Alexander,

Thank you so much for this information. The capacitive load from Micron SDRAM (MT48LC16M16A2) is 1.5pF min.. Considering trace parasitic capacitance, it is 1~3pF per inch. The total length of the trace is about 30mm. So the max. trace parasitic capacitance is 3pF max.. Plus the load capacitance, it is less than 5pF. The output resistance of 60X bus is 40 ohm per MPC8250 datasheet. With these fators, the simulation result showes that max. delay time is 200ps.  

Per MPC8250 hardware datasheet, SP30 is derived based on 50pF load, if the load capacitance is 5pF, SP30 will be further reduced.

Consider the above, MPC8250 timing does not meet the SDRAM's requirement.

I wonder in reality, as SP32 is 6.5ns, the average data retention after the 2nd rising edge of the clock is 3.5ns. That fully meets SDRAM's requirement. But I do not know the probability or CPK for this data so that I can assess the failure rate.

Thanks

John

[johnman]

Hi,

Continuous with the last reply. The Addr/data retenion time(SP30) from MPC8250 does not meet tAH,tDH time of MICRON SDRAM which are based on speed greed of -75, -7E with clock frequency is at 100MHZ~143MHZ. What about for a clock frequency of 66.67MHZ?

If these two parameter(tAH,tDH) are correlated with clock frequency, then with a lower clock frequency like 66.67MHZ, tAH and tDH may be longer, which could make MPC8250 meet the timing requirement.

Can you give me a comment?

Thanks

John

[alexander_yakov]

I do not think the same SDRAM chip (of the same partnumber), running at reduced frequency, will have reduced setup/hold time requirements. I expect these numbers will remain the same for all frequencies applied. 

[johnman]

Thanks.

[alexander_yakov]

Please do not forget about capacitive load connected to these pins, when you connect your SDRAM.

With 20pF capacitive load this 0.5ns will become 1ns.

Have a great day,
Alexander

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