MPC5674F External Multiplex Bus CS need Variable Wait State Access

[spetrofsky]

Most processors have an RDY signal line to tell the bus to hold until I am done.

Configuration:  A  MPC5674F processor EBI external Multiplexed mode using chip select Access.  

Problem:          If a peripheral tied to a single /CS on that external bus needs requires an extra  2-3 wait states only part of the time, and "0" wait for states the majority of the time.

QUESTION:      How do I tell the bus to extend add waits when the D_TA (bus acknowledge) signal is automatically internally generated.   

1. Can I override the D_TA to extend that bus access?
2. Pull another line to inform the processor that the bus transfer is not complete and need more time?

[davidtosenovjan]

Hi, I am afraid it is not possible. TA signal is explicitly defined as output or input, in accordance to SETA bit definition.

SETA Select External Transfer Acknowledge

0 Transfer Acknowledge (D_TA) is an output from the EBI, data phase will be terminated by the EBI.

1 Transfer Acknowledge (D_TA) is an input to the EBI, data phase will be terminated by an external device.

In case of using of FPGA, customers typically use externally terminated mode (SETA = 1) or non-CS access what’s the same from the point of view of TA usage just to have possibility to have various access times.