Input Pins configuration while reset activated

[jesusgonzalez]

Hello,

We are having problems with a MPC8306 input pins configuration while PORESETsignal is active. The issue is that pins configured as inputs are not acting as input as expected and they have a logic 1 value instead.

¿Any idea about what's happening?

Thanks in advance.:smileyblush:

[jesusgonzalez]

Any other sugestion?

[LPP]

There might be due to improper functioning of JTAG/COP port. Please, check if the port connections comply Freescale recommendations in AN4231 Design Checklist for MPC8306 Processor.

Critical things:

- PORESET should cause TRST

- pull-ups on TCK. It does not have an internal pull-up, and requires an external one if not used. There is a pullup on TMS but it is always safer to put a pullup on TCK however, because then we will not have a floating input.

.

[LPP]

Please, refer to section 2.2 "Power Sequencing" of MPC8306EC:

"if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up".

Have a great day,
Pavel

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[jesusgonzalez]

Just to clarify the situation:

PORESET is not a Power up reset but a warm reset initiated by user after system is steady.