How to reconfigure the MPC8315 boot ROM address?

[kennethhuang]

I am using an MPC8315 and a 64MB NOR flash in address 0xFC00_0000 to 0xFFFF_FFFF.  How do I boot from this NOR flash at the default 0xFF80_0000 to 0xFFFF_FFFF address and be able to reconfigure LAW0 to map its entire address space?  It seems the processor stopped whenever I changed LBLAWBAR0.  I do not have a NAND flash in another LAW as in the RDB.

[r8070z]

Have a great day,

Yes the code which programs local access window (LAW) should not be fetched from this window. It should set two 32-bit registers - the specified base address in one register should be aligned to the window size defined in the second. The core cannot set both LAW0 registers at once and at the same time uses it for routing to the elBC. You can initialize other local access window which covers memory with code for the LAW0 changing. Or the simplest way is using the second LAW for the FLASH. There can be up to 4 local access windows for the eLBC( LAW0..LAW3). So while code is executed in the 8-MBytes LAW0 window it can set LBLAWBAR1 for the FLASH start address and then set suitable size and enable local access window 1 in LBLAWAR1. Take into account that if two local access windows overlap, the lower numbered window takes precedence. So after that LAW0 is still in use.

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[kennethhuang]

Hi Serquei,

Thank you for the answer. I only have LCS0 connected to the flash in my hardware. All the other LCS are connected to different peripherals. I cannot use the other three LAW, which is essentially what the reference design does. Is there no other way to boot from a single flash (that is larger than 8MB) with the MPC8315?

Thanks.

[scottwood]

Put the initial boot code in the portion of flash that is mapped, then once DDR is initialized, copy code to it.  Once running from DDR, you can reconfigure the LAW.  See the U-Boot source for an example of this.

Alternatively, you could try running the code with instruction cache enabled, ensuring you don't cross a cacheline boundary while the LAW is in an invalid state, and that no cache line fetches occur to unmapped regions (not even speculatively).  The latter could possibly be achieved by doing the LAW change (including readback to sync) and an rfi to the new location all in one cacheline at the end of a page/block with the address of the next cacheline being unmapped or non-executable in the MMU.  But this is just an untested possibility -- using DDR is simpler (assuming you're enabling it anyway) and safer.

[kennethhuang]

Hi Scott,

Thank you for your answer. I found that I can remap the flash if I change (i.e. increase) the size first in LBLAWAR0 before changing the base address in LBLAWBAR0. This would keep the boot code in the LAW0 during the remapping. Otherwise, the boot code would be outside the LAW0 during the remapping if the base address was changed first before changing the size – as done in uboot.

Regards.