Have a great day,
The BRG provides a divide-by-16 option (BRGCn[DIV16]) and a 12-bit prescaler (BRGCn[CD]) to divide the source clock frequency. As combined source-clock factor they mean the BRG division factor (D) i.e. ratio of BRG input and output clock frequencies. Its value is given by expression
If BRGCx[DIV16]=1 then D = 16*(BRGCx[CD] + 1)
If BRGCx[DIV16]=0 then D = BRGCx[CD] + 1
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