Have a great day,
When the clock, control, command, and address buses have been routed in a fly-by topology, then each clock, control, command, and address pin on each DRAM is connected to a single trace. There is application note AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces on Freescale website.
This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem including fly-by topology.
In order to download it you can use search on top of any Freescale page. Or you can find link on Document tab of the MPC8569 Product summary page:
PowerQUICC III Processor with DDR2/3, eSDHC,|Freescale
The MPC8569MDS board uses SODIMM. DDR3 SODIMM layout can be example of the fly-by topolgy. Also DDR3 memory reference layouts can be found on JEDEC website. It requires registration. At last you can check internet for the layout example. See for instance
http://www.fedevel.com/welldoneblog/2011/02/ddr-ddr2-ddr3-pcb-layout-examples/
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
