thank you for your reply.
In my design:
sysclk = 100Mhz,
mpx clock ratio = 4:1 -> mpx clock = 400Mhz
DDR clock MCK = 200Mhz
DDR2 memory chip part number = MT47H128M16RT-25E IT:C
Is there any suggestion for ddr memory map set from the offset address 0x100 to 0x130?
I only use DDRC1 in the design and DDRC2 is not used.
I have two module under test now, the first one is ok in memory pattern test (all 1GB memory space has passed the test)and the second one has wrong bit on mdq5 and mdq16 occassionaly.
Please give me some advice to solve this problem.