Atomic Accesses

[mallen943]

The following is from EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors (EREF_RM Rev. 1 (EIS 2.1) 06/2014)

5.1.4 Atomic Accesses
A memory access is “single-copy atomic,” or simply “atomic,” if it is always performed in its entirety with no visible fragmentation. Atomic memory accesses are thus serialized: each happens in its entirety in some order, even when that order is not specified in the program or enforced between processors.

Vector accesses are not guaranteed to be atomic. The following other types of single-register accesses are always atomic:
      • Byte accesses (all bytes are aligned on byte boundaries)
      • Halfword accesses aligned on halfword boundaries
      • Word accesses aligned on word boundaries
      • Doubleword accesses aligned on doubleword boundaries

No other accesses are guaranteed to be atomic. For example, the access caused by the following instructions is not guaranteed to be atomic:
      • Any load or store instruction for which the operand is unaligned
      • lmw, stmw
      • Any cache management instruction

Does the above imply, given that a data word is aligned on a word boundary, the standard lwz/stw instructions would provide atomic access and therefore lwarx/stwcx instructions would not need to be used instead?

[June_Lu]

Single word boundary instruction is atomic access.

why would you use lwarx and stwcx? See my last reply. Lwarx should be paired with a later stwcx. to the same real address. Together they are Load and reserve and store conditional instructions. Word aligned lwz/stw could not reserve the data.

"Execution of a load and reserve or store conditional instruction to a misaligned address causes an alignment interrupt". From the statement misaligned could not use lwarx and stwcx. Load and reserve and store conditional sizes and addresses MUST match for a store conditional to be GUARANTEED to succeed, see Table 5-17.

[June_Lu]

The ability to emulate an atomic operation using lwarx and stwcx, Lwarx should be paired with a later stwcx. to the same real address. Together they are Load and reserve and store conditional instructions. Word aligned lwz/stw could not reserve the data. They are one instruction maybe atomic access, a lwz or a stw, could not work together. Also, please note EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors (EREF_RM Rev. 1 (EIS 2.1) 06/2014) page 266, NOTE: Software Considerations

"A misaligned lwz instruction which spans a page boundary for which one of the page translations is not in the TLB, can cause the access to be partially performed to one of the pages and also result in an a data TLB error (for the page translation not in the TLB)."

[mallen943]

My question wasn't regarding the pairing of instructions.  Simply, given what is stated in section 5.1.4 above, if a data word is aligned on a word boundary would the standard lwz and stw compiler generated instructions provide atomic access?  This is the question I need answered.

I understand there are specialized atomic versions of lwz and stw, which are lwarx and stwcx.  But if the answer to the above question is YES, then why would you use lwarx and stwcx?  My assumption was that these instructions would be used if the data word was not aligned.  However, section 5.6.1.2.8 of the EREF states, "Execution of a load and reserve or store conditional instruction to a misaligned address causes an alignment interrupt".

Thank you

[June_Lu]

Could share the MPU part number?

[mallen943]

T2080