For MPC8541, what is the maximum bit rate clock for SSI? Is it really 12.285MHz or can it be run up to platform clock / 8? Maximum bit rate clock for SSI is as per hardware spec i.e. 12.285MHz. This is the maximum speed at which the SSI IP is guaranteed to work. From a system perspective it is possible to clock it at a higher speed, but for MPC8541 that is not supported. If platform clock is 400MHz, please use appropriate values of DIV2, PSR and PM to ensure that the bit rate clock for SSI does not exceed 12.285MHz.

MPC8536 PCI controller can get clock from SYSCLK (synchronous) or from PCICLK (PCI asynchronous mode). If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCICLK, otherwise the processor will not boot up. Is this limit just due to PCI bus specs and if PCI is not used then MPC8536 PCI block can withstand 125MHz in synchronous mode? The PCI input clock frequency spec range is between 33 - 66MHz. IF the PCI interface is enabled, then this spec here will matter regardless whether you are running in synchronous or asynchronous mode. IF the PCI is disabled / un-used, it will not matter what input clock is being fed into this interface. Also, please refer to section 15.2 of the 8536 bring-up guide for termination details of the PCI pins including the PCI1_CLK pin when the interface is not being used. I am starting 8536 design making use of both SerDes serial interfaces: 1) SerDes1: PCI Express 1 (x4) (2.5 Gbps) → SerDes1 Lanes A-D; PCI Express 2 (x1) (2.5 Gbps) → SerDes1 Lanes E-F 2) SerDes2: SATA1 → SerDes2 Lane A. Each SerDes has its own reference clock. They will both run at 100MHz. Are there any phase requirements between these 2 clocks? There is no requirement on 8536 for any particular phase relationship between reference clock for Serdes 1 vs Serdes 2 because each serdes is completely independent.

MPC8535 PCI controller can get clock from SYSCLK (synchronous) or from PCICLK (PCI asynchronous mode). If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCICLK, otherwise the processor will not boot up. Is this limit just due to PCI bus specs and if PCI is not used then MPC8535 PCI block can withstand 125MHz in synchronous mode? The PCI input clock frequency spec range is between 33 - 66MHz. IF the PCI interface is enabled, then this spec here will matter regardless whether you are running in synchronous or asynchronous mode. IF the PCI is disabled / un-used, it will not matter what input clock is being fed into this interface. Also, please refer to section 15.2 of the 8535 bring-up guide for termination details of the PCI pins including the PCI1_CLK pin when the interface is not being used. I am starting 8535 design making use of both SerDes serial interfaces: 1) SerDes1: PCI Express 1 (x4) (2.5 Gbps) → SerDes1 Lanes A-D; PCI Express 2 (x1) (2.5 Gbps) → SerDes1 Lanes E-F 2) SerDes2: SATA1 → SerDes2 Lane A. Each SerDes has its own reference clock. They will both run at 100MHz. Are there any phase requirements between these 2 clocks? There is no requirement on 8535 for any particular phase relationship between reference clock for Serdes 1 vs Serdes 2 because each serdes is completely independent.

MPC8360 H/W spec describes that Max SYSCLK frequency is 100MHz. Generically when user inputs 100MHz clock, actual clock speed become more faster. I think MPC8360 has enough margin for faster SYSCLK as long as I use up to 100MHz oscillator. Is my understanding correct? Yes, your understanding is correct. As long as you use 100MHz oscillator it should be fine.

For MPC8308 package, which is the GTX clock pin for TSEC1 and TSEC2? According to the MPC8308 ballmap, V21 is the GTX clock pin of TSEC1 and T19 is the GTX clock pin of TSEC2. Can a spread spectrum clock be used for the 66.66 Mhz DDR clock of the MPC8308? If so what percentage spread is allowed and what modulation frequency? Yes, a spread spectrum clock can be used for 66.66 Mhz DDR clock. Please refer to below table for details: Spread Spectrum Clock Source Recommendations Parameter Min Max Unit Frequency modulation — 60 kHz Frequency spread — 1.0  %

Does MPC8306 come with SerDes clocks enabled? Will MPC8306 remain in reset if the SERDES is enabled and no SerDes reference clock is available? Yes, MPC8306 comes with SerDes clocks enabled. However, MPC8306 doesn't wait for SERDES PLL lock for it to come out of reset. For MPC8306, which jitter spec (tCLK_DJ, tCLK_TJ or tCLK_DJ+tCLK_TJ) should the buffer and oscillator require to meet? The input jitter at the SD_REF CLK input is specified, Buffer vendor will have to provide jitter at the output in pk-to-pk terms so that it can be compared with the Tj at SD_REF CLK input What is the relationship between RMS jitter and peak-to-peak jitter in MPC8306? How can I calculate the RMS jitter value from our peak-to-peak jitter value (42 ps and 86 ps)? RMS jitter is only valid for Random (Gaussian distribution) jitter. This rms value is then converted to pk-to-pk value and added to Deterministic jitter (pk-to-pk) for finding the total jitter (in pk-to-pk). For SD_REF CLK, the HW specs state the value for Total jitter (in peak to peak ps) and Deterministic jitter (in peak to peak ps). rms value for Rj can be referred from PCI Express™ Jitter and BER Revision 1.0. Converting the rms to pk-to-pk is not going to help here because the buffer datasheet states the additive phase jitter. This is measured by integrating the phase noise over the frequency band of interest. DDR. “In asynchronous mode, the memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR PLL rate." Is this statement correct for MPC8306? No it is not correct. The correct statement is " In asynchronous mode, if the ratio of the DDR data rate to the CCB clock rate is greater than 3 :1 ( i.e. DDR=3:CCB=1 ), than the DDR performance monitor statistic accuracy cannot be guaranteed."