Whether FS6523 assert FS0B low when a external reset detected

[Jamber_H]

During FS6523 running normally in debug mode, an external reset is assert by MCU, whether FS6523 assert FS0B low in this condition?

In user manual Fail Safe Machine, external reset will set the SBC to Release RST phase, in the picture, it said FSxB assert low, is it means FS6523 will assert FS0B low if an external reset occured?

Best Regards

Jamber

[JozefKozon · Accepted solution]

Dear Jamber,

please refer to section 11.16 in the FS45/FS65 datasheet. The behavior of the FS0B and FS1B outputs in debug mode are the same as in normal mode. So the answer is yes. FS0B will be low if the external reset occurs.

With Best Regards,

Jozef