PF5020 Detailed Bit-Field Descriptions Not in Datasheet

[Shivani_Elavena]

Dear NXP Community,

I am currently working with both the PF5020 and PF8100 PMICs in our embedded system design. While I have reviewed the latest datasheets for both devices, I found that they lack detailed descriptions for each register’s bit-fields, and specific functionality.

For example, while the datasheets mention registers addresses and high-level functions (e.g., SW1_RUN_MODE, OTP_FSS_EN), they don’t explain what each bit means, how to safely modify them, or what the default values are after reset or OTP loading.

I have also reviewed related documents, including:

• PF5020, PF8100 Datasheet 

Despite this, I’m still missing the complete register map with detailed bit-level descriptions, and I couldn't find a register reference manual similar to what's often available for MCUs or SoCs.

Could you please advise on the following:

1. Is there a register reference guide or internal documentation with full bit-field breakdowns for PF5020 and PF8100

2. Are there any additional technical resources or application notes that provide deeper explanation of the register functions and OTP settings?

Thank you for your support.

Best regards,
Shivani

[james698cross]

Hello @Shivani_Elavena,
Great question. Unfortunately, NXP hasn’t published a full register reference guide with bit-level breakdowns for the PF5020 and PF8100 PMICs. Some OTP bit descriptions are embedded in the datasheets, but detailed internal documentation isn’t publicly available. You may want to contact NXP support directly for more in-depth insights or application notes.

Best Regards,
James Cross

[TomasVaverka]

Dear Mr. Elavena,

Unfortunately there is no additional documentation with a detailed OTP registers bit description you may know from our SBC datasheets such as FS26, sorry about that.

However, you can actually find a description of the OTP bits in the datasheets.

OTP_FSS_EN bit:

SW1_RUN_MODE:

BRs, Tomas