PF0100 discharge question

[m_c]

Customer is doing stress test for their i.MX 6Quad digital cluster which power on PF0100 VIN for 3900ms then off for 100ms repeatedly.
Then found the i.MX 6Quad didn’t power up after 8 hours and can’t reset even set PF0100 PWRON to low then high manually (follow i.MX 6Quad SABRE reset SW2 design).
After discuss with NXP PMIC FAE, suspect the cause may because PF0100 didn’t discharge completely, so can't make sure which mode is in state diagram.
Therefore ask customer to measure the discharge time of all output pins which longest is 369ms.
Then NXP FAE ask customer to do more experiments that extend the on-off time.
1. Customer increase on-off period more than 100ms, then found the fail possibility is decreased.
2. Customer increase on-off period more than 500ms, then found the issue didn’t happened after 8 hours.

Customer would like to know why PF0100 can't reset by set PWRON to low then high manually when i.MX 6Quad didn't power up just because it didn't fully discharged?

[m_c]

Sorry for misleading the issue to PWRON, please allow me to describe issue again.
If customer power on VIN for 3900ms and off for 100ms, then PF0100 will not output voltage after 8 hours.
If cusotmer power on VIN for 3500ms and off for 500ms, then PF0100 will still output voltage after 8 hours.
The longest discharge time of all output pins is 369ms.
Customer would like to know why discharge is not complete, which will affect the situation that PF0100 can't output voltage.

[JozefKozon · Accepted solution]

Dear Mike, 

All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. 

JozefKozon_0-1679556315582.png

The capacitors on the VCORDIG, VCOREF and VCORE together with the decoupling capacitors on the regulator outputs needs to be discharged to successfully turn off the regulators. 

JozefKozon_1-1679556462821.png

JozefKozon_2-1679556478491.png

With Best Regards,

Jozef

[m_c]

Where can we find more detail explaination or block diagram or schematic of block of reference gerneration?

[JozefKozon]

Dear Mike, 

I am not sure, if I understand your request. Could you please elaborate? Most of the relevant information can be found in the PF0100 datasheet. Please find additional documents I have found on my PC disk.

With Best Regards,

Jozef

[JozefKozon]

Dear Mike, 

please also check the MMPF0100 Errata. Has the customer the older PF0100 or newer the PF0100A? 

JozefKozon_0-1679401466105.png

With Best Regards,

Jozef

[JozefKozon]

Dear Mike, 

please check how has the customer set the PWRON_CFG bit and the PWRONRSTEN bit. 

JozefKozon_0-1679400224990.png

By default it should be set both of them to 0. The PWRON_CFG to level sensitive. 

JozefKozon_2-1679400780129.png

JozefKozon_1-1679400730305.png

But if the customer has set the PWRON_CFG to 1, edge sensitive, to properly turn off the PMIC, the PWRON pin must be held low for at least 4s and the PWRONRSTEN must be set to 1. Please refer to the Figure 8. in the MMPF0100 datasheet. 

JozefKozon_3-1679401036458.png

With Best Regards,

Jozef