MC3377ASP1 AFE is Burning

[S_Abhishek]

Hi Everyone,

I am using MC33774SP1 AFE for my BMS application. I am using it for cell voltage measurement, cell balancing [external+internal] on my board. I am using it for 15s battery pack though i have designed it for 18 cells. I am shorting the last three terminals to make it as 15s. I am facing AFE burning issues in which Vbat and ground pins are getting short and fire is getting observed on IC. I am attaching my schematic for your reference as well. Could you please guide me related to this.

Also, I am using a wakeup circuitry for my BMS in between VBAT and VSTACK pins.

[TomasVaverka]

Hi,

Using the MC33774ASP1 in a 15s configuration is possible, but the unused upper channels must be connected correctly. For a 15s stack, the active cell connections should use CT0 to CT15 and CB0 to CB15. The unused upper pins should be connected to the highest used cell node, meaning CT16, CT17 and CT18 should be tied to CT15, and CB16, CB17 and CB18 should be tied to CB15.

One important concern from the schematic is the VBAT/VSTACK connection. It appears that VBAT is supplied from VSTACK through diode circuitry. Please note that VBAT must closely track the highest CT/CB cell node. In particular, the voltage difference between VBAT and the highest CB node must remain within the datasheet limits. If the diode path or wake-up circuitry creates a voltage drop or transient difference between VSTACK/highest CT/CB and VBAT, this could overstress the device.

Please check the following points before continuing powered tests:

1. Confirm that CT16, CT17 and CT18 are tied locally to CT15, and CB16, CB17 and CB18 are tied locally to CB15 for the 15s configuration.
2. Confirm that VBAT is connected to the actual top-of-stack node through the recommended VBAT filter and that the wake-up circuit does not introduce a diode drop or transient offset between VBAT and the highest CT/CB node.
3. Measure VBAT, VSTACK, CT15 to CT18, and CB15 to CB18 during pack connection, wake-up and power-up. The transient behavior is important, not only the steady-state voltage.
4. Confirm that balancing and measurement are disabled for the unused upper channels.
5. Confirm that the external balancing MOSFET circuitry for the unused channels cannot create any unintended current path.
6. Please also verify the capacitor values on the CT/CB sensing lines. If large capacitors are used on each cell tap, the inrush current during pack connection may cause transient overstress.

Based on the destructive nature of the failure, with VBAT and ground becoming shorted and visible IC damage, this should be treated as a possible hardware overstress condition. I recommend stopping further powered tests until the VBAT/VSTACK relationship and the unused-cell connections are verified with measurements.

BRs, Tomas