platform: mcu fs32k144, SPI communication to MC33771B.
a.wakeup mc33771 for BCS Pin.
b.Reset mc33771 for Write mc33771 SYS_CFG1.(not respond)
c.Assign CID for Write mc33771 INIT.(not respond)
Problem: from the appearance point of view, there is no corresponding command for Mc33771.
Logical analysis shows that the data has been sent according to the standard.
What's going on here!
Hi,
There are some things you should take care about:
- On the MC33771, SPI communication is enabled using the SPI_COM_EN pin. To select SPI communication, the SPI_COM_EN pin must be terminated to the VCOM supply. Make sure this is true.
* Systems using only SPI communication to the 33771 may leave RDTX_OUT+ and RDTX_OUT– unterminated or may short them to ground.
- The CSB wake-up capability imply some system considerations when SPI communication is used. Assumed the CSB line is pulled up to the same power supply used by the MCU. When the MCU commands the 33771 to go sleep and then the MCU itself goes to sleep, both devices sleep until the time the MCU wakes up. However, when this happens, the 33771 wakes up, because the CSB line transitions from low state to high state. To avoid this behavior, the MCU has to take care to force the CSB line to the high state during the entire sleep time.
- SPI interface termination depends on the SPI interface voltage you are using in your system, check image for details:
- One 40-bit register of previously requested data is retrieved through serial out for each current serial in message sent by the MCU. For message integrity and communication robustness, each SPI transmit message consists of six fields containing 40 bits. The six transmit fields are defined as following:
- Cyclical redundancy check (8 bits)
- Command field (4 bits)
- Cluster ID field (4 bits)
- Memory address field (7 bits)
- Master/slave field (1 bit), always at 1 in the response.
- Memory data field (16 bits)
Messages having less or more than 40 bits, incorrect CRC, or incorrect SCLK/RDTX_IN– phase are disregarded. Communication faults set the COM_ERR_FLT fault bit in the FAULT1_STATUS register and increments the COM_STATUS[COM_ERR_COUNT] register.
Note: It is required that the SCLK/RDTX_IN– input is low before the falling edge of CSB (SCLK/RDTX_IN– phase).
- On power-up (POR) or RESET (pin) or SYS_CFG1[SOFT_RST], the 33771 device only responds to the cluster ID of 0000. The user must change the cluster ID of the device by writing a new cluster ID into register INIT[CID]. Subsequent read/write command must use the new cluster ID to communicate to the device. Whatever the type of transmitted message, the master has to write a logic 0 in the master/slave bit. The 33771 ignores messages having the master/slave bit at logic 1.
Notes:
- In SPI communication, global write commands are not allowed and the 33771 responds with an all zero message with the correct CRC in the subsequent message frame.
- In SPI communication, the 33771 responds with all zero and the correct CRC to the very first 33771/ MCU message frame.
