LBIST issue with MC33FS6500LAE

[jasperimmanuel]

Hello @AllanAn ,

One of customer is facing below issue with regards to MC33FS6500LAE PMIC :

1. During first power up, all of the voltage rails (Vpre,Vcca,Vaux) show an under-voltage bit being set in diagnostic registers- ONLY first time read. Subsequently when the registers are read there is no under-voltage that is set (except VAUX- this is expected as VAUX is not being used). Why do we see initial under voltage in all voltage rails ?
2. The LBIST fault remains to show in the BIST Register every time the register is being read.

We are not able to determine the reason for the LBIST error as no such clear causes are mentioned in the documentation with regards to the chip.

Please find the waveforms attached below of the start-up Sequence:

• Waveform 1:

1. VSUP (Sluggish behavior is due to Power supply)
2. VPRE
3. Select Line
4. VCORE

• Waveform 2:

1. VPRE
2. Select Pin
3. VCORE
4. Interrupt line

Kindly let me know what is causing the initial undervoltage and LBIST error ?

Regards,

Jasper Raj Immanuel

[AllanAn]

Hi Jozef, 1. It is OK that UV bits reported every time the device power up, as all regulators are Under voltage at first. It is device behavior. 2. For LBIST Issue, Please make sure there is no SPI read error, how about the A-B(Change a new FS65 device in the board) test result ? LBIST will pass when fail-safe machine, stuck fault >90% coverage. Brs Allan

[jasperimmanuel]

Hello @allan 

Customer has provided below feedback and follow up query :

Kindly find below the update and further query wrt to our application:

1. LBIST Failure: as mentioned in the mail below.
2. We went into isolating each part of the SBC to check which peripheral could be causing the issue.
3. On isolating the IO-2 and IO-3 pin, the LBIST failure seems to be cleared.
4. In our application, the IO-2 and IO-3 Pins are default pulled High. On studying the datasheet it was observed that the IO_23_FS bit of the INIT_FSSM register is default set to safety critical.

1. The Suspect would be; that since the Pins are being pulled high (Default), the LBIST is being triggered and hence being treated as a failure.

Future Steps:

1. Would our analysis (as mentioned above) hold true wrt to the LBIST being set?
2. If this is the case, the LBIST failure would occur, during every Power on Reset and hence the module would fail.
3. The idea for the work-around: the LBIST Failure during the first power on cycle would be ignored and during initialization the IO_23_FS bit would be configured as “0” i.e. NOT SAFETY and hence configuring IO2 and IO3 as wake-up inputs as required by our application.
4. After initialization, The normal mode would be entered (after good WD refresh)
5. Query: Would the IO_23_FS bit hold its value after wake-up from LPOFF mode and LBIST would not be triggered? (system sleep mode is where is cut off the 5V supply).

• Query: With the LBIST fault being set, is it possible to pass the Fail safe state machine to normal mode after good WD Refresh?

Kindly provide your feedback,

Regards,
Jasper

[AllanAn · Accepted solution]

Hi Jasper,

1. What's the voltage level of IO2,IO3 when device powerup ?

2. When IO2  voltage is 12V during device powerup,fail safe machine will stop and device will enter test mode, ABIST1 will fail. after IO2 go down, fail safe state machine will continue and ABIST1 will pass.

3. so our datasheet says max rating of IO2/IO3 is 8V, please make sure IO2/IO3 voltage are below 8V during powerup.

4.  If LBIST fail during device powerup, it will not stop RSTB release and MCU can send SPI command to SBC, but FS0B/FS1B will not be released due to LBIST fail.

Brs

Allan