I plan to use MMPF0100 F0 mode. (Part MMPF0100F0ANES)
I plan to use the VREFDDR voltage follower feature for DDR3(L) instead of using resistors as a voltage divider for DDR_VREF
The datasheet for PF0100's VREFDDCRTL register on page 26, it says:
"Enable or disables VREFDDR output voltage • 0 = VREFDDR Disabled • 1 = VREFDDR Enabled "
And under the "Default" column the setting is 0x0
However the Device Start-up Configuration page (18) shows both the 'Default configuration' and 'F0' modes having the VREFDDR_SEQ set to '3' with no mention of it being enabled or disabled.
Q1: Is the VREFDDR output disabled for modes 'default' and 'F0' or will it come up at sequence 3?
Q2: If it is disabled, is the intention for the controlling device (U-Boot) to start up using sram alone, contain PFUZE100 drivers and devicetree and enable VREFDDR?
Q3: If it is disabled, which other part number of PF0100 has it enabled by default?
