FS4500 SBC FS0b release not worked

[phanendravarma_]

Hello,

I'm not able to release FS0b pin.Its always low.

Please find the attached snapshots of register values and help me to identify the problem.

Note:In sbc init ,after first watchdog refresh watchdog was disable by selecting watchdog window as 0.

Errors Observed: VSNS_UV=1, FS0B_SNS=0, RSTB_EXT=1, FLT_ERR=6,SPI_REQ=1

[TomasVaverka · Accepted solution]

Hi,

Watchdog disable (WD_WINDOW_3:0 = 0b0000) is effective only when the INIT_FS phase is closed, so it requires at least one good watchdog refresh (0x4D when using a default LFSR value of 0xB2) within the 256 ms of the INIT_FS timeout.

Best regards,

Tomas

[phanendravarma_]

Hi Tomas,Thanks for the reply

Now, I activated periodic watchdog refreshes and FS0b line is released.But still i encountered below errors in driver:

VSNS_UV=1,RSTB_EXT=1,SPI_REQ=1

Input to sbc is always 12v then why VSNS_UV is set?

In Init part of driver ,DIAG_VSUP_VCAN register is readed to clear it ,even though why VSNS_UV is set?.

In which scenarios SPI_REQ bit will be set?

what is the meaning for RSTB_EXT(External) set?

Thanks,

PVR

[TomasVaverka]

Hi,

VSNS_UV bit in the DIAG_VSUP_VCAN register is an image of Vbat. After a POR, VSNS crosses VSNS_UV and consequently VSNS_UV flag is set:

As you correctly stated, reading DIAG_VSUP_VCAN register (0x2000) is required after a POR to clear this flag. Are you sure you are reading this register correctly during the initialization phase?

SPI_REQ indicates an invalid SPI access:

Best regards,

Tomas

[phanendravarma_]

Hi, 

1.Reading DIAG_VSUP_VCAN verified by SPI_G bit and communication was successful. 

But some how VSNS_UV was not cleared .

Is there is any other check points?

2.what is the meaning for RSTB_EXT(External) set?