serdes PLL timeout at P1020 POR configuration

[hyoungkikim]

hello  experts

i  am desiging a board  with P1020

i have a question

in P2020  Design Checklist  ( AN4261, Page 9)

TRIG_OUT is used to configure  SerDes PLL clock timeout  to prevent boot-up hang-out

but P1020 Design Checklist  , there is no commnet about SerDes PLL clock timeout

in P1020   if SerDes clock isn't used   SerDes PLL clock timeout  happen  so there is no boot-up hang-out

or do i have to set POR-configruation pin 

i can't find  any infomation   if i miss some thing  please advice me

thank you

[hyoungkikim]

thank you

[r8070z · Accepted solution]

Have a great day,

According to the P1020 datasheet TRIG_OUT must be pulled-up. In this case the P1020 can boot if no SerDes clock is applied to the P1020.

Unofficially I knew case when on a P1020/P2020 board the P1020 was installed and it was found that

"if cfg_srds_pll_toe = 0, pulled down, no SerDes clock input to P1020, P1020 fail to boot.

if cfg_srds_pll_toe = 1, pulled up, no SerDes clock input to P1020, P1020 can boot up."

where cfg_srds_pll_toe is on TRIG_OUT pin during the poreset in case of the P2020. But again for the P1020 this pin must be high during poreset.

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