codewarrior connect P2020RDB

[zhongjian]

I use codewarrior(CW for power architecture(TM V8.8)) connect P2020RDB.  Emulator is CodeWarrior USB TAP.

When I use debug to connect, codewarrior gave a error information("Fail to reset the target Draco/m HIP8:ELF is not in expected HALT mode").

How can we fix this problem?

[yipingwang]

CodeWarrior 8.8 is used for P2020RDB-PA and PB with DDR2, for P2020RDB-PC, it is recommended to use CodeWarrior 10.3.

Would you please share your CCS log? Please enable ccs log from "Debug Version Settings->Remote Debug->Edit Connection->Enable logging".

[zhongjian]

Follow file is ccs log.

CCS: 0000	:	ccs_open
CCS:		:		ipaddr = 127.0.0.1
CCS:		:		port = 41475
CCS:		:		timeout = 10
CCS:		:		serverh = 0
CCS:		:	ccs_open; ccs_error = 10
CCS:		:		Error message:

Connection refused

CCS: 0000	:	ccs_open
CCS:		:		ipaddr = 127.0.0.1
CCS:		:		port = 41475
CCS:		:		timeout = 10
CCS:		:		serverh = 0
CCS:		:	ccs_open; ccs_error = 0
CCS: 0000	:	ccs_get_connection_count
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_get_connection_count; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_delete_cc
CCS:		:		serverh = 0
CCS:		:		count = 0
CCS:		:	ccs_delete_cc; ccs_error = 0
CCS: 0000	:	ccs_config_cc
CCS:		:		serverh = 0
CCS:		:		config_string = utap:0
CCS:		:	ccs_config_cc; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_available_connections
CCS:		:		serverh = 0
CCS:		:		count = 1
CCS:		:	ccs_available_connections; ccs_error = 0
CCS: 0000	:	ccs_set_timeout
CCS:		:		serverh = 0
CCS:		:		timeout = 10
CCS:		:	ccs_set_timeout; ccs_error = 0
CCS: 0000	:	ccs_config_server
CCS:		:		serverh = 0
CCS:		:		cc = 0
CCS:		:		server_config = 0
CCS:		:		value = 4030
CCS:		:	ccs_config_server; ccs_error = 0
CCS: 0000	:	ccs_get_config_chain
CCS:		:		serverh = 0
CCS:		:		device_list: (size = 0)
CCS:		:	ccs_get_config_chain; ccs_error = 0
CCS: 0000	:	ccs_config_chain
CCS:		:		serverh = 0
CCS:		:		cc = 0
CCS:		:		device_list: (size = 1)
CCS:		:			device[0]:: core_type=102;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:	ccs_config_chain; ccs_error = 0
CCS: 0000	:	ccs_get_config_chain
CCS:		:		serverh = 0
CCS:		:		device_list: (size = 3)
CCS:		:			device[0]:: core_type=0;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:			device[1]:: core_type=0;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:			device[2]:: core_type=0;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:	ccs_get_config_chain; ccs_error = 0
CCS: 0000	:	ccs_get_config_chain
CCS:		:		serverh = 0
CCS:		:		device_list: (size = 3)
CCS:		:			device[0]:: core_type=102;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:			device[1]:: core_type=53;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:			device[2]:: core_type=53;	device_descr=[ir_length:0;dr_bypass_length:0;bypass_instruction:0]
CCS:		:	ccs_get_config_chain; ccs_error = 0
CCS: 0000	:	ccs_send_message
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		message = 3
CCS:		:	ccs_send_message; ccs_error = 0
CCS: 0000	:	ccs_reset_to_debug
CCS:		:		serverh = 0
CCS:		:		cc = 0
CCS:		:	ccs_reset_to_debug; ccs_error = 0
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 2032
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0xfffffffc
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 63
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0xffff0000
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 63
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0xffff0000
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 415
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x0000f000
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 415
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x0000f000
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 406
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x0000f700
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 406
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x0000f700
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 312
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0xfffffffc
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 312
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0xfffffffc
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 308
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x40800000
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 308
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x40800000
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 309
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x00000000
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 309
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x00000000
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 2034
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x02000200
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 2034
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x02000200
CCS:		:	ccs_read_reg; ccs_error = 0; duration=0 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 308
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x40800000
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_read_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 2034
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x02000200
CCS:		:	ccs_read_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_write_reg
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		index = 308
CCS:		:		count = 1
CCS:		:		value: (size = 1)
CCS:		:			0x41800000
CCS:		:	ccs_write_reg; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_out
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		ccs_io addr: (size = 4)
CCS:		:			0x00000000 0x00007531 0x00000000 0x00000000
CCS:		:		value: (size = 8)
CCS:		:			00000000 00000200
CCS:		:	ccs_out; ccs_error = 0; duration=1 ms
CCS: 0000	:	ccs_run_core
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:	ccs_run_core; ccs_error = 0
CCS: 0000	:	ccs_stop_core
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:	ccs_stop_core; ccs_error = -2147418097
CCS:		:		Error message:

ELF is not in expected HALT mode

CCS: 0000	:	ccs_get_messages
CCS:		:		coreh = [serverh:0;cc_index:0;chain_pos:1]
CCS:		:		message: (size = 0)
CCS:		:	ccs_get_messages; ccs_error = 0
CCS: 0000	:	ccs_delete_cc
CCS:		:		serverh = 0
CCS:		:		count = 0
CCS:		:	ccs_delete_cc; ccs_error = 0
CCS: 0000	:	ccs_kill_server
CCS:		:		serverh = 0
CCS:		:	ccs_kill_server; ccs_error = 0

[marius_grigoras]

Hi,

It seems to be a problem with stopping the core after reset to debug and run.

After reset, the e500v2 core nee to run before being able to enter in debug mode. That's why we implemented a work-around in the initialization file: set a HW BP at reset address and run the core, after the core hits the BP, it enters in debug mode.

The mandatory condition is to have a valid opcode at the interrupt vector. In CW classic, there was an assumption that a valid opcode already exists due to u-boot/ROM code resides in the reset space, but of course this is not happening all the time.

Can you please switch to PA10.3 as Yiping already suggested? In PA10.3 this WA is correctly implemented using the SRAM area.

Regards,

Marius